Xilinx HDMI 1.4 Product Manual page 47

Video Resolution Horizontal Total Horizontal Active Vertical Total Vertical Active
1080p60
Pixel clock represents the total number of pixels need to be sent every second. Therefore,
Pixel clock = Htotal × Vtotal × Frame Rate
=2200 x 1125 x 60
=148,500,000
= 148.5Mhz
Link clock = (Data clock)/4=222.75/4=55.6875Mhz
Video clock = (Pixel clock)/PPC=148.5/2=74.25Mhz
Data clock = Pixel clock × BPC/8=148.5× 12/8=222.75Mhz
Using the associative property in this example,
Data clock = 222.75Mhz < 340Mhz
then
TMDS clock = Data clock = 222.75Mhz
Figure shows how the clock is distributed in HDMI TX Subsystem and the relationship to
the Video PHY Controller.
X-Ref Target - Figure 3-11
Audio interface
(axis_audio_aclk)
Video interface opt 1
(axis_video_aclk)
Video interface opt 2
(video_clk)
CPU interface
(AXI4-lite)
Figure 3‐11: HDMI Transmitter Subsystem and Video PHY Controller
The HDMI TX Subsystem is able to support either AXI4-Stream Video or Native Video.
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
2200 1920
TX Subsystem
AXI4-S
to
Video
Bridge
Video
Timing
Controller
AXI4
Interconnect
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Video Phy Controller
Link Data
vid_phy_tx_axi4s
Link Clock
HDMI TX
txoutclk
Core
video_clk
tx_video_clk
HDCP
(optional)
Designing with the Subsystem
Frame Rate
(Hz)
60
TMDS data
phy_tx_out[2:0]
TMDS clock
tx_tmds_clk
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