Xilinx HDMI 1.4 Product Manual page 91

X-Ref Target - Figure C-3
START
IP Initialization and
Callback Setup
HDMI TX:
HPD Assert Intr?
N
SW start/
change video?
N
HDMI TX:
TX Stream Up
Intr?
N
HDMI TX:
Vertical Sync
Intr?
N
B
Application Integration
Figure C-4 shows an example code on how an HDMI 1.4/2.0 Transmitter Subsystem can be
used in your application.
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Y
Update VPHY TX Reference
clock
Y
Program external clock
generator
Y
IF STREAM_UP:
peripheral &
Y AUX interrupt
IF STREAM_DOWN:
Disable AUX
peripheral &
Send InfoFrame,
AUX interrupt
General Control
Packets &
Vendor-specific
InfoFrame
Configure HDMI Retimer
Enable TX TMDS output
Configure Audio
Figure C‐3: TX Flow
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Appendix C: Application Software Development
Enable AUX
chip (if needed)
clock buffer
Reset TX DDC
Disable VPHY TMDS output
buffer when HPD is asserted
Enable VPHY TMDS output
buffer when HPD is released
X#####-093017
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