Xilinx HDMI 1.4 Product Manual page 30

bits wide. The valid signal is driven High when the CTS and N parameters are stable. For
more information, see Chapter 7 of the HDMI 1.4 specification
On the rising edge of the valid signal, the TX reads the CTS and N parameters from the ACR
input interface and transmits an audio clock regeneration packet.
Table 2-5 shows the Audio Clock Regeneration (ACR) interface signals. This interface runs at
the s_axis_audio_aclk clock rate.
Table 2‐5: Audio Clock Regeneration (ACR) Interface
Name
acr_cts
acr_n
acr_valid
If a HDMI system does not require audio, tie the following input ports to LOW:
• AUDIO_IN (except tready)
• s_axis_audio_aresetn
• s_axis_audio_aclk
• acr_cts
• acr_n
• acr_valid
When multiple channel audio is enabled in the system, ensure that the audio data is
IMPORTANT:
properly sent to their perspective channel allocation. Unused channels must be packed with zero (i.e.
Mute) to avoid audio channel swapping, which means audio data may appear in unexpected channel
locations.
The L-PCM (Packet Type 0x02) allows you to pack up to 24 bits of audio from the Audio Data
Note:
Stream. The HBR (Packet Type 0x09) allows you to pack up to 16 bits of audio from the Audio Data
Stream. The data is taken from MSB (bit 27:12). Compressed Audio (IEC 61937) can also be sent the
same as L-PCM data (IEC60958). However, it is your responsibility to compress the audio data and
uncompress the data audio with your custom logic.
L-PCM (IEC60958) Audio is the only Audio format tested on board by Xilinx only in
IMPORTANT:
Example Design.
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Direction Width
Input 20
Input 20
Input 1
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Chapter 2: Product Specification
[Ref 12].
Description
CTS
N
Valid
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