Resets - Xilinx HDMI 1.4 Product Manual

When AXI4-Stream is selected, the video stream is sent to HDMI TX Subsystem
°
through Video Interface in AXI4-Stream format running at axis_video_aclk. The
AXI4-Stream is then processed and converted into Native Video stream by
AXI4-Stream to Video Out Bridge core with the help of Video Timing Controller
module. Because the AXI4-Stream carries only active video data, the AXI4-Stream to
Video Out core takes input from an AXI4-Stream slave interface and converts it into
a Native Video stream, which is then fed to the HDMI TX core. The HDMI TX Core
then pack the native video data with Audio data and other auxiliary data into Link
Data and sent to Video PHY Controller at Link Clock.
When Native Interface is selected, Video stream is sent to HDMI TX Subsystem as
°
native video and directly passed to HDMI TX core. The data are then packed and
binded with Audio data and other auxiliary data into Link Data and sent to Video
PHY Controller at Link Clock.
Based on the system requirement, Video PHY Controller is generating Link Clock and
Video Clock for HDMI TX Subsystem for each targeted video resolution. Meanwhile, the
axis_audio_aclk, axis_video_aclk, and AXI4-Lite clocks are free running clocks
in the system usually generated by clock wizard with reference to some on-board
oscillators.

Resets

Each AXI interface has its own reset signal. The reset signals, s_axi_cpu_aresetn,
s_axis_video_aresetn and s_axis_audio_aresetn are for S_AXI_CPU_IN,
VIDEO_IN (AXI4-Stream Video Interface), and AUDIO_IN respectively. These three reset
signals are active-Low. Because the reset signal is used across multiple sub-blocks in the
subsystem, keep the system in the reset state until all the clocks are stabilized. You can use
the locked signal from the clock generation block as a reset signal.
There is no dedicated hardware reset for VIDEO_IN interface when Native Video interface is
Note:
selected. However, HDMI TX Subsystem outputs a video_rst signal, which you can use to reset its
Native Video Source generation modules.
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Chapter 3:
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Designing with the Subsystem
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