Xilinx HDMI 1.4 Product Manual page 79

X-Ref Target - Figure A-2
HDMI Source
HDMI RX
Subsystem
Table A-1, Table
the release for different video formats. The following limitations apply:
• When Number of pixels per clock on AXI4-S output (PPC) set to 4, only video
formats with total horizontal resolution divisible by 4 are supported. For example, a
video resolution 720p60 has horizontal total pixel 1650, which is not divisible by 4.
Therefore, it can't be supported in the design with PPC set to 4.
Table A‐1: Tested Video Resolutions for RGB 4:4:4 and YCbCr 4:4:4
Resolution
480i60
576i50
1080i50
1080i60
480p60
576p50
720p50
720p60
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Appendix A: Verification, Compliance, and Interoperability
Video PHY Controller
Video to
AXI4-
Stream
Generator
Bridge
MicroBlaze/
Zynq-7000 SoC/
Zynq US+
Native Video
AXI4-Stream
Video
AXI-Lite
Figure A‐2: Test Setup for Native Video Interface
A-2, and Table A-3 show the video resolutions that were tested as part of
Horizontal
Total Active
858 720
864 720
2640 1920
2200 1920
858 720
864 720
1980 1280
1650 1280
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AXI4-
Test
Stream
Pattern
to
Video
Bridge
UART
I2C
Vertical
Total
525
625
1125
1125
525
625
750
750
HDMI Sink
HDMI TX
Subsystem
X16568-033016
Frame
Rate (Hz)
Active
480 60
576 50
1080 50
1080 60
480 60
576 50
720 50
720 60
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