Xilinx HDMI 1.4 Product Manual page 63

X-Ref Target - Figure 5-3
KC705/KCU105/ZC706 Evaluation Kit
TB-FMCH-HDMI4K
Cable Driver
HDMI TX
(DP159)
Clock Gen
OSC
(Si5324)
reference clock in
tx-only mode
HDMI RX
Oscillator
Figure 5‐3: C705/KCU105/ZC706 HDMI Reference Design Clock and Datapath Diagram
X-Ref Target - Figure 5-4
ZCU102 Evaluation Kit
HDMI 2.0 Circuitry
Cable Driver
HDMI TX
(DP159)
Clock Gen
OSC
(Si5324)
reference clock in
tx-only mode
HDMI RX
Oscillator
Figure 5‐4: ZCU102 HDMI Reference Design Clock and Datapath Diagram
In pass-through mode, the VPHY Controller core recovers the high-speed serial video
stream, converts it to parallel data streams, forwards it to the HDMI_RX_SS core, which
extracts the video and audio streams from the HDMI stream and converts it to separate AXI
video and audio streams. The AXI video goes through the TPG core and the AXI audio goes
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
FPGA
Video PHY
Controller
tx_tmds_clk_p/n
tx_tmds_data(2:0)
tx_gtrefclk clock p/n
reference clock in
pass-through mode
rx_tmds_clk_p/n
rx_gtrefclk clock p/n
rx_tmds_data(2:0)
nidru gtrefclk clock p/n
FPGA
Video PHY
Controller
tx_tmds_clk_p/n
tx_tmds_data(2:0)
tx_gtrefclk clock p/n
reference clock in
pass-through mode
rx_tmds_clk_p/n
rx_gtrefclk clock p/n
rx_tmds_data(2:0)
nidru gtrefclk clock p/n
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txoutclk
tx_video_clk
TX
tx_tmds_clk
axis_tx_tmds_data_ch(2:0)
rxoutclk
rx_video_clk
RX
rx_tmds_clk
axis_rx_tmds_data_ch(2:0)
txoutclk
tx_video_clk
TX
tx_tmds_clk
axis_tx_tmds_data_ch(2:0)
rxoutclk
rx_video_clk
RX
rx_tmds_clk
axis_rx_tmds_data_ch(2:0)
Chapter 5: Example Design
axis_audio
HDMI TX
axis_video
Subsystem
Test
Audio
Pattern
Generator
Generator
HDMI RX
Subsystem
axis_video
axis_audio
axis_audio
HDMI TX
axis_video
Subsystem
Test
Audio
Pattern
Generator
Generator
HDMI RX
Subsystem
axis_video
axis_audio
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