Xilinx HDMI 1.4 Product Manual page 65

X-Ref Target - Figure 5-6
zynq_ss/zynq_us_ss
Processor
System Reset
Module
Clock Wizard
AXI interconnect (AXI lite)
audio_ss
Audio Pattern
Gen
Figure 5‐6: HDMI Reference Design Block Diagram (Zynq or Zynq UltraScale+)
Example Design Specifics
In addition to the Video PHY Controller, HDMI Transmitter Subsystem and HDMI Receiver
Subsystem core, the complete example design includes the following cores:
• MicroBlaze or Zynq or Zynq UltraScale+
• MicroBlaze Debug Module (Only for MicroBlaze based processor subsystem)
• AXI Interconnect
• Local Memory Bus (Only for MicroBlaze based processor subsystem)
• LMB BRAM Controller (Only for MicroBlaze based processor subsystem)
• Block Memory Generator (Only for MicroBlaze based processor subsystem)
• Clocking Wizard
• Processor System Reset
• AXI UARTLite (Only for MicroBlaze based processor subsystem)
• AXI Interrupt Controller (Only for MicroBlaze based processor subsystem)
• AXI IIC
• AXI GPIO
• Video Test Pattern Generator
• AXI4-Stream Register Slice
• Utility Buffer
• Utility Vector Logic
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
DDR
UART
ZYNQ or
ZYNQ UltraSCALE+
tpg_ss
Clock Wizard HDMI ACR AXI GPIO
www.xilinx.com
Chapter 5: Example Design
HDMI HDMI
Test Pattern
Transmitter Receiver
Generator
Subsystem Subsystem
Send Feedback
FPGA IO
AXI IIC
Video PHY
Controller
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