Clocks And Resets - Xilinx HDMI 1.4 Product Manual

Clocks and Resets

Table 2-12 provides an overview of the clocks and resets. See
Chapter 3 for more information.
Table 2‐12: Clocks and Resets
Name
s_axi_cpu_aclk
s_axi_cpu_aresetn
s_axis_video_aclk
s_axis_video_aresetn
s_axis_audio_aclk
s_axis_audio_aresetn
link_clk
video_clk
Notes:
1. The reset should be asserted until the associated clock becomes stable.
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Direction Width
Input 1
Input 1
Input 1
Input 1
Input 1
Input 1
Input 1
Input 1
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Chapter 2: Product Specification
Clocking
Description
AXI4-Lite CPU control interface clock.
Reset, associated with s_axi_cpu_aclk
(active-Low). The s_axi_cpu_aresetn signal
resets the entire subsystem including the data
path and AXI4-Lite registers.
AXI4-Stream video input clock.
Reset, associated with s_axis_video_aclk
(active-Low). Resets the AXI4-Stream data path
for the video input.
AXI4-Stream Audio input clock. (The audio
streaming clock must be greater than or equal
to 128 times the audio sample frequency)
Reset, associated with s_axis_audio_aclk
(active-Low). Resets the AXI4-Stream data path
for the audio input.
HDMI Link data output clock. This connects to
the Video PHY Controller Link clock output.
Clock for the native video interface.
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