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Xilinx HDMI 1.4 Product Manual

Xilinx HDMI 1.4 Product Manual

Logicore ip hdmi 1.4/2.0 transmitter subsystem
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HDMI 1.4/2.0
Transmitter Subsystem
v3.0
LogiCORE IP Product Guide
Vivado Design Suite
PG235 October 4, 2017

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Summary of Contents for Xilinx HDMI 1.4

  • Page 1 HDMI 1.4/2.0 Transmitter Subsystem v3.0 LogiCORE IP Product Guide Vivado Design Suite PG235 October 4, 2017...

  • Page 2: Table Of Contents

    Video Resolutions ..............77 HDMI 1.4/2.0 TX Subsystem...
  • Page 3 Finding Help on Xilinx.com ........

  • Page 4: Ip Facts

    IP Facts Introduction LogiCORE™ IP Facts Table Subsystem Specifics The HDMI 1.4/2.0 Transmitter Subsystem is a UltraScale+™ Families (GTHE4) hierarchical IP that bundles a collection of UltraScale™ Architecture (GTHE3) Supported HDMI® TX IP sub-cores and outputs them as a Zynq®-7000 All Programmable SoC...

  • Page 5: Chapter 1: Overview

    Chapter 1 Overview The HDMI 1.4/2.0 Transmitter Subsystem is a feature-rich soft IP incorporating all the necessary logic to properly interface with PHY layers and provide HDMI® encoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI TX-related IP sub-cores and outputs them as a single IP.

  • Page 6: Licensing And Ordering Information

    100 Mhz, the IP times out after approximately 4 hours of normal operation when Hardware Evaluation License is being used. License Type This Xilinx® LogiCORE™ IP module is provided under the terms of the Xilinx Core License Agreement. The module is shipped as part of the Vivado® Design Suite. For full access to all subsystem functionalities in simulation and in hardware, you must purchase a license for the subsystem.

  • Page 7: Chapter 2: Product Specification

    (Video Timing Controller and AXI4-Stream to Video Out Bridge) to construct HDMI TX Subsystem to be able to supportAXI4-Stream based video. By performing this, HDMI TX Subsystem is able to work seamlessly with other Xilinx video processing IP cores. HDMI 1.4/2.0 TX Subsystem...
  • Page 8 Video Interface is selected as video interface. In this illustration, both HDCP 1.4 and HDCP 2.2 are selected and both Video over AXIS compliant NTSC/PAL Support and Video over AXIS compliant YUV420 Support are selected. The HDMI 1.4/2.0 Transmitter Subsystem supports two types of video interface: • AXI4-Stream Video Interface •...
  • Page 9 The audio clock regeneration architecture is not part of the HDMI TX subsystem. You must provide an audio clock to the application. This can be achieved by using an internal PLL or external clock source, depending on the audio clock requirements, audio sample frequency HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 10 Two underlining subcore API drivers are called to set the above two SCDC bits with respect to the video stream to sent. • XV_HdmiTx_Scrambler(InstancePtr->HdmiTxPtr); is to used to: Enable HDMI TX scrambler for HDMI 2.0 video and disable scrambler for HDMI 1.4 ° video stream. Update scrambler bit in Sink's TMDS Configuration register °...
  • Page 11 The packet body, graphically represented in Figure 2-5, is made from four subpackets; each subpacket includes 56 bits (7 bytes) of data and 8 bits (1 byte) of BCH ECC parity. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 12 Figure 2‐5: Packet Body Notes: 1. ECC is calculated in HDMI 1.4/2.0 Transmitter Subsystem core. Therefore, must construct HB0…HB2, and PB0, PB1…PB26, PB27 according to HDMI specs in the software. 2. When calculating the checksum value (PB0), the ECC values are ignored.
  • Page 13 HDMI TX Vsync interrupt callback. void XV_HdmiTxSs_SendGenericAuxInfoframe(XV_HdmiTxSs *InstancePtr, void *Aux) where, InstancePtr is a pointer to HDMI TX Subsystem instance. ° Aux is a 36 byte array contains the complete AUX packet. ° HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 14 Pixel Packing Phase and Color depth information are retrieved from video stream and sent through general control packet by the driver. However, AVMUTE and Default_Phase fields are not updated and remain as zero always. X-Ref Target - Figure 2-7 HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 15 Color space and VIC information are retrieved from video stream and sent through AVI Infoframe. Other fields are not updated and remain as zero always. X-Ref Target - Figure 2-8 HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 16 X-Ref Target - Figure 2-9 HDCP As part of the HDMI TX Subsystem, the Xilinx® LogiCORE™ IP High-bandwidth Digital Content Protection (HDCP™) transmitters are designed for transmission of audiovisual content securely between two devices that are HDCP capable. In this HDMI TX Subsystem, both HDCP 1.4 and HDCP 2.2 Transmitter IP cores are included.

  • Page 17: Standards

    HDCP v2.2 Product Guide (PG249) [Ref 25]. Standards The HDMI 1.4/2.0 Transmitter Subsystem is compliant with the AXI4-Stream Video Protocol and AXI4-Lite interconnect standards. See the Vivado AXI Reference Guide (UG1037) [Ref 1] for additional information. Also, see HDMI specifications [Ref 12].

  • Page 18: Performance And Resource Utilization

    Chapter 2: Product Specification The Xilinx HDCP 2.2 is compliant with the HDCP 2.2 specification entitled High-bandwidth Digital Content Protection, Mapping HDCP to HDMI, Revision 2.2, issued by Digital Content Protection (DCP) LLC [Ref 13]. Performance and Resource Utilization For full details about performance and resource utilization, visit the...

  • Page 19: Port Descriptions

    Port Descriptions Figure 2-11 Figure 2-14 show the HDMI 1.4/2.0 Transmitter Subsystem ports when AXI4-Stream is selected as video interface. The VIDEO_IN port is expanded in the figure to show the detail AXI4-Stream Video bus signals. The following subsystem has three default interfaces: •...
  • Page 20 Chapter 2: Product Specification X-Ref Target - Figure 2-12 Figure 2‐12: HDMI TX Subsystem Pinout – AXI4-Stream Video Interface (HDCP 1.4 Only) HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 21 Chapter 2: Product Specification X-Ref Target - Figure 2-13 Figure 2‐13: HDMI TX Subsystem Pinout – AXI4-Stream Video Interface (HDCP 2.2 Only) HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 22 (HDCP 1.4 and HDCP 2.2) Figure 2-15 Figure 2-18 show the HDMI 1.4/2.0 Transmitter Subsystem ports when Native Video is selected as video interface. The VIDEO_IN port is expanded in the figure to show the detail Native Video bus signals.
  • Page 23 VIDEO_IN LINK_DATA2_OUT VIDEO_IN_tdata[3*BPC*PPC-1:0] link_clk VIDEO_IN_active_video VIDEO_IN_hsync DDC_OUT VIDEO_IN_vsync video_rst SB_STATUS_IN s_axi_cpu_aclk s_axi_cpu_aresetn s_axis_audio_aclk s_axis_audio_aresetn acr_cts[19:0] acr_n[19:0] acr_valid video_clk Figure 2‐15: HDMI TX Subsystem Pinout – Native Video Interface (No HDCP) HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 24 Chapter 2: Product Specification X-Ref Target - Figure 2-16 Figure 2‐16: HDMI TX Subsystem Pinout – Native Video Interface (HDCP 1.4 Only) HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 25 VIDEO_IN_active_video VIDEO_IN_hsync DDC_OUT VIDEO_IN_vsync video_rst SB_STATUS_IN hdcp22_irq hdcp22_timer_irq s_axi_cpu_aclk s_axi_cpu_aresetn s_axis_audio_aclk s_axis_audio_aresetn acr_cts[19:0] acr_n[19:0] acr_valid video_clk X16564-032516 Figure 2‐17: HDMI TX Subsystem Pinout – Native Video Interface (HDCP 2.2 Only) HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 26 HDCP14_KEY_IN hdcp22_irq hdcp22_timer_irq acr_cts[19:0] acr_cts[19:0] acr_n[19:0] acr_n[19:0] acr_valid acr_valid video_clk video_clk Figure 2‐18: HDMI TX Subsystem Pinout – Native Video Interface (HDCP 1.4 and HDCP 2.2) HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 27 S_AXI_CPU_IN_arvalid Input Read address valid S_AXI_CPU_IN_aready Output Read address ready S_AXI_CPU_IN_rdata Output Read data S_AXI_CPU_IN_rresp Output Read data response S_AXI_CPU_IN_rvalid Output Read data valid S_AXI_CPU_IN_rready Input Read data ready HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 28 Chapter 2: Product Specification Video Input Stream Interface This HDMI 1.4/2.0 Transmitter Subsystem is supporting two types of video input stream interfaces, which eventually is mapped to HDMI 1.4/2.0 Transmitter Subsystem VIDEO_IN interface. • AXI4-Stream Video interface • Native Video Interface Table 2-2 shows the signals for AXI4-Stream video input streaming interface.
  • Page 29 3. When native video interface is selected, there is no hardware reset. 4. You must provide the correct video timing information. You can choose to use Xilinx Video Timing Controller (vtc) or design your own vtc module to generate the timing control signals for native video interface.
  • Page 30 L-PCM data (IEC60958). However, it is your responsibility to compress the audio data and uncompress the data audio with your custom logic. L-PCM (IEC60958) Audio is the only Audio format tested on board by Xilinx only in IMPORTANT: Example Design.
  • Page 31 Table 2‐8: HDCP 1.4 Key Input Interface Name Direction Width Description HDCP_KEY_IN_tdata Input HDCP 1.4 key data HDCP_KEY_IN_tlast Input End of key data HDCP_KEY_IN_tready Output Ready HDCP_KEY_IN_tuser Input Start of key data HDCP_KEY_IN_tvalid Input Valid HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 32 HDCP 2.2 interrupt output ports. Table 2‐9: HDCP 2.2 Interrupt Output Interface Name Direction Width Description hdcp22_irq Output HDCP 2.2 interrupt hdcp22_timer_irq Output HDCP 2.2 timer interrupt HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 33 Active High. However, if you add an inverter to the HPD signal, then the HPD polarity must be set to Active Low in HDMI Transmitter Subsystem GUI. Miscellaneous Signals with Native Video Interface Table 2-11 shows the miscellaneous signals with native video interface selected. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 34 Therefore, in the PCB, if you choose to use a voltage divider or level shifter, the HPD polarity remains as Active High. However, if you add an inverter to the HPD signal, then the HPD polarity must be set to Active Low in HDMI Transmitter Subsystem GUI. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...

  • Page 35: Clocks And Resets

    Input the Video PHY Controller Link clock output. video_clk Input Clock for the native video interface. Notes: 1. The reset should be asserted until the associated clock becomes stable. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 36: Chapter 3: Designing With The Subsystem

    X-Ref Target - Figure 3-1 Figure 3‐1: Audio Cycle In HDMI 1.4/2.0 Transmitter Subsystem, the number of Audio Channels is set through the software driver. You must enable the correct number of audio channel according to your use case and send the corresponding audio channel data mapping to the channel ID (TID). For HDMI 1.4/2.0 TX Subsystem...
  • Page 37 8 channel audio, then you must set Audio Channel number to 8 in HDMI 1.4/2.0 Transmitter Subsystem driver. Then, the corresponding audio data must be prepared and sent to HDMI 1.4/2.0 Transmitter Subsystem in the hardware, as described in Figure 3-1.
  • Page 38 Per Component set in the Vivado IDE, all bits are transported with the MSB aligned and the remaining LSB bits are padded with 0. This applies to all Max Bits Per Component settings. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 39 AXI4-Stream video protocol. A data format for a fully compliant AXI4-Stream video protocol with dual pixels per clock is illustrated in Figure 3-5. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 40 However the current data format is not complaint with the AXI4-Stream video protocol. Figure 3-6 Figure 3-7 show the data format for quad and dual pixels formats. X-Ref Target - Figure 3-6 Figure 3‐6: YUV420 Color Space Quad Pixels Data Format HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 41 X-Ref Target - Figure 3-8 Figure 3‐8: YUV 4:2:0 AXI4-Stream Video Data (Dual Pixel per Clock) However, in the native HDMI video interface, the video data representation must be as shown in Figure 3-9. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 42: Interlaced Video

    X-Ref Target - Figure 3-9 Figure 3‐9: Native HDMI Video Interface Therefore, a remapping feature is added to HDMI 1.4/2.0 Transmitter Subsystem to convert HDMI native video into AXI4-Stream video. For RGB/YUV444/YUV422 formats, video data is directly mapped from AXI4-Stream to Native Note: Video interface without any line buffer.
  • Page 43 • When Native Interface is selected, the native video stream must be prepared and fed to the Video_In port of the HDMI 1.4/2.0 Transmitter Subsystem, which is directly connected to the HDMI TX core inside the HDMI 1.4/2.0 Transmitter Subsystem.
  • Page 44 • Pixel repetition is only available for AXI4-Stream Interface After it is enabled in the HDMI 1.4/2.0 Transmitter Subsystem, you must prepare interlaced video as normal, then the HDMI 1.4/2.0 Transmitter Subsystem replicates each pixel twice before sending the data out.

  • Page 45: Clocking

    Chapter 3: Designing with the Subsystem each pixel twice. When the video is sent out by the HDMI 1.4/2.0 Transmitter Subsystem, it is sent as two fields of 1440x240 @ 30Hz video. Clocking The S_AXI_CPU_IN, VIDEO_OUT, and AUDIO_OUT can be run at their own clock rate. The HDMI link interfaces and native video interface also run at their own clock rate.
  • Page 46 GT devices, calculate the clock frequencies and make sure the targeted device is able to support it. When using the HDMI 1.4/2.0 Transmitter Subsystem with Xilinx Video PHY Controller IP core, more information can be found in Video PHY Controller LogiCORE IP Product Guide (PG230) [Ref 24].
  • Page 47 HDCP (optional) CPU interface AXI4 Interconnect (AXI4-lite) Figure 3‐11: HDMI Transmitter Subsystem and Video PHY Controller The HDMI TX Subsystem is able to support either AXI4-Stream Video or Native Video. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 48: Resets

    There is no dedicated hardware reset for VIDEO_IN interface when Native Video interface is Note: selected. However, HDMI TX Subsystem outputs a video_rst signal, which you can use to reset its Native Video Source generation modules. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 49: Chapter 4: Design Flow Steps

    This section includes information about using Xilinx tools to customize and generate the subsystem in the Vivado Design Suite. The HDMI 1.4/2.0 Transmitter Subsystem can be added to a Vivado IP integrator block design in the Vivado Design Suite and can be customized using IP catalog. For more...
  • Page 50 Video Interface: This option selects the Video Interface for the HDMI TX subsystem. The allowable options are AXIS-Stream or Native Video. Include HDCP 1.4 Encryption: This option enables HDCP 1.4 encryption. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 51 High or Low. HDCP 1.4 and 2.2 Encryption options are only configurable if you have a HDCP license, else it Note: is disabled and greyed out from the GUI. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 52 FIFO, and at least 16 less than the number of active video lines. FIFO Depth: Specifies the number of locations in the input FIFO. The allowable values are 32, 1024, 2048, 4096, and 8192. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 53 Tx Only showcases the HDMI system built with only one HDMI TX Subystem and Video PHY Controller. A Frame CRC helper core is added to the Tx Only topology to facilitate system monitor and debugging. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 54 GUI. The Open Example Design is not supported for Native Video Interface. Therefore, the IMPORTANT: Example Design Tab is not available when Native Video is selected. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 55 Include (Tick) TRUE Max bits per component C_MAX_BITS_PER_COMPONENT Number of pixels per clock on Video C_INPUT_PIXELS_PER_CLOCK Interface Hot Plug Detect Active C_HPD_INVERT High High High Video Bridge Hysteresis Level C_HYSTERESIS_LEVEL HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 56 QPLL(GTXE2) QPLL01(GTHE3/4) Include NIDRU C_EXDES_NIDRU true Include (Tick) true Exclude (Untick) false Output Generation For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 16]. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 57: Constraining The Subsystem

    For more information on the device constraint/dependency, see the Video PHY Controller LogiCORE IP Product Guide (PG230) [Ref 24]. Table 4-2 shows the device and speed grade selections for HDMI 1.4/2.0 Transmitter Subsystem. Table 4‐2: Device and Speed Grade Selections Device Family...
  • Page 58 HDMI 2.0 UltraScale –2 Notes: 1. All HDMI 1.4 resolutions can be supported. 2. Full HDMI 2.0 resolutions support up to 4096 x 2160 @ 60fps. Clock Frequencies The AXI4-Lite CPU clock must run at 100 Mhz. See Clocking in Chapter 3 for more information.

  • Page 59: Simulation

    Simulation of the subsystem is not supported. Synthesis and Implementation For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 16]. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 60: Summary

    This chapter contains step-by-step instructions for generating an HDMI Example Design from the HDMI 1.4/2.0 Transmitter Subsystem by using Vivado® Flow. Summary HDMI 1.4/2.0 Transmitter Subsystem allows users to customize the example design based on their system requirements. It offers the full flexibility with the following system parameters: Topology: •...
  • Page 61 • ZCU102 Evaluation Board Hardware The example design is built around the HDMI 1.4/2.0 Transmitter Subsystem (HDMI_TX_SS), HDMI 1.4/2.0 Receiver Subsystem (HDMI_RX_SS) (Optional), Video PHY (VPHY) Controller core and leverages existing Xilinx IP cores to form the complete system. Figure 5-1...
  • Page 62 The VPHY Controller core has been configured for the HDMI application that allows transmission and reception (optional) of HDMI video/audio to and from the HDMI 2.0 daughter card or on-board HDMI 2.0 circuitry. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 63 HDMI stream and converts it to separate AXI video and audio streams. The AXI video goes through the TPG core and the AXI audio goes HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 64 HDMI HDMI Audio Pattern Test Pattern Video PHY Clock Wizard HDMI ACR AXI GPIO Transmitter Receiver Generator Controller Subsystem Subsystem Figure 5‐5: HDMI Reference Design Block Diagram (MicroBlaze) HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 65 AXI Interrupt Controller (Only for MicroBlaze based processor subsystem) • AXI IIC • AXI GPIO • Video Test Pattern Generator • AXI4-Stream Register Slice • Utility Buffer • Utility Vector Logic HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 66: Running The Example Design

    Running the Example Design 1. Open the Vivado Design Suite and create a new project. 2. In the pop-up window, press Next until you get to the page to select Xilinx® part or board for the project. X-Ref Target - Figure 5-7 3.
  • Page 67 Chapter 5: Example Design You can rename the IP component name, which is used as example design project ° name. 6. Configure HDMI 1.4/2.0 Transmitter Subsystem, then click OK. X-Ref Target - Figure 5-8 HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 68 7. Click on Generate. a. You may optionally click Skip if you just want to generate the example design. 8. Right click on the HDMI 1.4/2.0 Transmitter Subsystem component under Design source, and click Open IP Example Design. 9. Choose the target project location, then click OK.
  • Page 69 14. Create Board Support Package in Vivado SDK. 15. Enter BSP project name and click Finish. 16. Click OK. 17. From system.mss, find the HDMI 1.4/2.0 Transmitter Subsystem and click on Import Examples. 18. Select xhdmi_example. HDMI 1.4/2.0 TX Subsystem...
  • Page 70 HDCP Key Utility An optional hdcp_key_utility application software is available for using the same hardware to program your own HDCP encryption keys into the EEPROM (FMC or on-board). To hdcp_key_utility application: HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 71 You should now have 1 x 8 byte KSV + 40 x 8 byte Keys. 3. Byte swap each 8 byte set to reverse their order (convert from Little-endian to Big-endian). HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 72 Use the following steps to execute the system using generated bitstream and software elf from the example design 1. Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx Design Tools > Vivado 2017.3 > Vivado 2017.3 Tcl Shell.
  • Page 73 COM port associated with the CP210x, is the one connected to the KCU105 board system controller and the standard COM port is the one connected to the FPGA UART. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 74 Migration Notes When migrating from version 2016.3 or earlier, make note of the following: • Hot Plug Detect Active has been added to HDMI 1.4/2.0 Transmitter Subsystem GUI. Choose High in the Example Design (according to board design). • Hot Plug Detect Active has been added to HDMI 1.4/2.0 Receiver Subsystem GUI.
  • Page 75 You can enabled/disable it by selecting "h" from UART menu. • System log is moved from direct UART printout to event log. You can display the event log by selecting "z" from UART menu. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 76: Appendix A: Verification, Compliance, And Interoperability

    Inrevium Artix-7 FPGA ACDC A7 Evaluation Board • Zynq®-7000 All Programmable SoC evaluation board (ZC706) • ZCU102 Evaluation Board The HDMI 1.4/2.0 Transmitter Subsystem is tested with the following sink devices: • Quantum Data 980B • Quantum Data 780B •...

  • Page 77: Video Resolutions

    The Test Pattern Generator can also be configured to generate certain video pattern in the AXI4-Stream video format, which can be used to test the HDMI TX Subsystem alone instead of relying on the video received from the HDMI RX Subsystem. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 78 This is because the Test Pattern Generator can be configured to generate certain video pattern in AXI4-Stream video format, which can be used to test the HDMI TX Subsystem alone instead of relying on the video received from the HDMI RX Subsystem. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...
  • Page 79 Vertical Frame Resolution Rate (Hz) Total Active Total Active 480i60 576i50 1080i50 2640 1920 1125 1080 1080i60 2200 1920 1125 1080 480p60 576p50 720p50 1980 1280 720p60 1650 1280 HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 80 Rate (Hz) Total Active Total Active 1080i50 2640 1920 1125 1080 1080i60 2200 1920 1125 1080 480p60 576p50 720p50 1980 1280 720p60 1650 1280 1080p24 2750 1920 1125 1080 HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 81 1050 Table A‐3: Tested Video Resolutions for YCbCr 4:2:0 at 8, 10, 12, 16 Bits/Component Horizontal Vertical Frame Resolution Rate (Hz) Total Active Total Active 2160p60 4400 3840 2250 2160 HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 82: Appendix B: Debugging

    TIP: Chapter 1 for more details. Finding Help on Xilinx.com To help in the design and debug process when using the HDMI 1.4/2.0 Transmitter Subsystem, the Xilinx Support web page contains key resources such as product documentation, release notes, answer records, information about known issues, and links for obtaining further product support.

  • Page 83: Debug Tools

    Xilinx Support web page. Debug Tools Tools are available to address HDMI 1.4/2.0 Transmitter Subsystem design issues. It is important to know which tools are useful for debugging various situations. Vivado Design Suite Debug Feature The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into your design.

  • Page 84: Hardware Debug

    Appendix B: Debugging Reference Boards Various Xilinx development boards support the HDMI 1.4/2.0 Transmitter Subsystem. These boards can be used to prototype designs and establish that the subsystem can communicate with the system. • 7 series FPGA evaluation board KC705 °...

  • Page 85: Interface Debug

    • The s_axi_aclk and aclk inputs are connected and toggling. • The interface is not being held in reset, and s_axi_areset is an active-Low reset. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 86 To ensure that the audio is working in HDMI 1.4/2.0 Transmitter Subsystem, the AXI4-Stream must be constructed as described below. The HDMI 1.4/2.0 Transmitter Subsystem supports up to 8 audio channels. The audio data is transmitted through AXI4-Stream audio interface, which is a customized AXI4-Stream protocol that is used to send audio samples with sideband signals defined in AES3 specification.
  • Page 87 If 8 channel audio is enabled in your design, only 6 out of 8 channels carry valid audio data. For the unused channels, you must pack the audio data with zeros and the sub-frame data allocation follows as per illustrated above. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017...

  • Page 88: Appendix C: Application Software Development

    Appendix C Application Software Development Device Drivers The HDMI 1.4/2.0 Transmitter Subsystem driver abstracts the included supporting elements and provides you with an API for control. The API can be easily integrated into your application thereby providing an out-of-the-box solution.
  • Page 89 Sub-Core IPn Driver Figure C‐1: Subsystem Driver Architecture The HDMI 1.4/2.0 Transmitter Subsystem is a MAC subsystem which works with a Video PHY Controller (PHY) to create a video connectivity system. The HDMI 1.4/2.0 Transmitter Subsystem is tightly coupled with the Xilinx Video PHY Controller, which itself is independent and offer flexible architecture with multiple-protocol support.
  • Page 90 The HDMI 1.4/2.0 Transmitter Subsystem provides a set of API functions for application code to use. On top of that, when HDMI 1.4/2.0 Transmitter Subsystem hardware interrupts are generated, the subsystem driver is invoked to configure the system accordingly. HDMI 1.4/2.0 Transmitter Subsystem provides callback structure to hook up your own callback...
  • Page 91 Configure Audio X#####-093017 Figure C‐3: TX Flow Application Integration Figure C-4 shows an example code on how an HDMI 1.4/2.0 Transmitter Subsystem can be used in your application. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 92 X-Ref Target - Figure C-4 Figure C‐4: Application Example Code To integrate and use the HDMI 1.4/2.0 Transmitter Subsystem driver in your application, the following steps must be followed: 1. Include the subsystem header file xv_hdmitxss.h that defines the subsystem object.
  • Page 93 XV_HDMITXSS_KEY_HDCP14 XV_HDMITXSS_KEY_HDCP22_LC128 (128-bit DCP Licensed Constant) 2. Initialize the HDMI 1.4/2.0 Transmitter Subsystem driver after the HDCP keys have been loaded. Initializing the subsystem begins the HDCP 1.4/2.2 drivers internally. 3. Connect the HDCP interrupt handlers to the interrupt controller interrupt ID: HDMI 1.4/2.0 TX Subsystem...
  • Page 94 XV_HdmiTxSs_HdcpPushEvent ° XV_HDMITXSS_HDCP_AUTHENTICATE_EVT 8. Check the status of authentication. These checks could be performed before issuing authentication requests. HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 95 ° Integrate Video PHY Controller Driver for HDMI TX Subsystem Usage Because the HDMI 1.4/2.0 Transmitter Subsystem is closely coupled with the Video PHY Controller, the following example code demonstrates how a Video PHY Controller can be used in your application.
  • Page 96 X-Ref Target - Figure C-5 Figure C‐5: Application Example Code To integrate and use the Video PHY Controller for HDMI 1.4/2.0 Transmitter Subsystem in the application code, the following steps must be followed: 1. Include the subsystem header file xvphy.h that defines the subsystem object.
  • Page 97 Steps are shown in the previous section and not repeated here. Interrupts All interrupts generated by the HDMI 1.4/2.0 Transmitter Subsystem are listed here: 1. HPD – Peripheral I/O to detect HDMI cable 5.0V signal a. Rising edge – Cable connected b.
  • Page 98 API: int XV_HdmiTxSs_SetCallback(XV_HdmiTxSs *InstancePtr, u32 HandlerType, void *CallbackFuncPtr, void *CallbackRef); Available handlers are defined in xv_hdmitxss.h: • XV_HDMITXSS_HANDLER_CONNECT • XV_HDMITXSS_HANDLER_VS • XV_HDMITXSS_HANDLER_STREAM_UP • XV_HDMITXSS_HANDLER_STREAM_DOWN • XV_HDMITXSS_HANDLER_HDCP_AUTHENTICATE HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 99 *Aux); XV_HDMITXSS_HANDLER_STREAM_UP This interrupt is triggered every time the Video PHY Controller is reconfigured and the output clock is stabilized and ready for HDMI 1.4/2.0 Transmitter Subsystem to transmit video stream. The callback function needs to perform the following: 1.
  • Page 100 Appendix C: Application Software Development void XVphy_Clkout1OBufTdsEnable(XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Enable); 3. Set HDMI 1.4/2.0 Transmitter Subsystem Sampling Rate with the Video PHY Controller TX Sampling Rate. void XV_HdmiTxSs_SetSamplingRate(XV_HdmiTxSs *InstancePtr, u8 SamplingRate); XV_HDMITXSS_HANDLER_STREAM_DOWN This interrupt is triggered every time the Video PHY Controller is reconfigured and the output clock is not stable for HDMI 1.4/2.0 Transmitter Subsystem to stream video.
  • Page 101 Follow the steps in Chapter 5, Example Design to create an example design, which contains all the procedures implemented and can serve as a reference for integrating the HDMI 1.4/ 2.0 Transmitter Subsystem into your system. Example Use Cases In this section, some typical use cases are illustrated with how system reacts at run time to certain events and what is expected for you to perform.
  • Page 102 Appendix C: Application Software Development Use Case 4: Send Video Stream 1. Disable the Video PHY Controller TDMS clock for HDMI 1.4/2.0 Transmitter Subsystem through API: XVphy_Clkout1OBufTdsEnable(XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Enable); Example: XVphy_Clkout1OBufTdsEnable(VphyPtr, XVPHY_DIR_TX, (FALSE)); 2. Set the HDMI 1.4/2.0 Transmitter Subsystem stream parameters through API:...
  • Page 103 If you enable 8 channel audio in your design, only 6 out of 8 channels are used to carry Note: valid audio data. For the unused channels, you must pack the audio data with zeros by muting them. XhdmiAudGen_SetPattern(&AudioGen, 7, XAUD_PAT_MUTE); HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...
  • Page 104 API XV_HdmiTxSs_SendGenericAuxInfoframe to send out. Use Case 6: Enable HDMI Mode Use the following API: XV_HdmiTxSS_SetHdmiMode(&HdmiTxSs); XV_HdmiTxSs_AudioMute(&HdmiTxSs, FALSE); Use Case 7: Enable DVI Mode Use the following API: XV_HdmiTxSS_SetDviMode(&HdmiTxSs); XV_HdmiTxSs_AudioMute(&HdmiTxSs, TRUE); HDMI 1.4/2.0 TX Subsystem Send Feedback PG235 October 4, 2017 www.xilinx.com...

  • Page 105: Appendix D: Additional Resources And Legal Notices

    Support. Documentation Navigator and Design Hubs Xilinx Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado IDE, select Help > Documentation and Tutorials.

  • Page 106: References

    References These documents provide supplemental material useful with this product guide: 1. Xilinx Vivado AXI Reference Guide (UG1037) 2. Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) 3. Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) 4.

  • Page 107: Revision History

    • Added example design migration notes. 10/05/2016 • Added example design flow. • Added HPD XGUI option. • Added software use cases. • Updated Xilinx AUTOMOTIVE APPLICATIONS DISCLAIMER. 06/08/2016 • Updated optional video over AXI-Stream support. 04/06/2016 • Added Features section in IP Facts.

  • Page 108: Please Read: Important Legal Notices

    Xilinx’s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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