Xilinx HDMI 1.4 Product Manual page 46

Table 3‐3: Clocking
Clock
Source synchronous clock
TMDS to HDMI interface (This is
clock the actual clock on the
HDMI cable).
This is the actual data rate
clock. This clock is not used
Data
in the system. It is only
clock
listed to illustrate the clock
relations.
Clock used for data
Link interface between HDMI
clock PHY Layer Module and
subsystem
This is the internal pixel
clock. This clock is not used
Pixel
in the system. It is only
clock
listed to illustrate the clock
relations.
Video Clock used for video
clock interface
Notes:
1. The examples in the Example column are only for reference and do not cover all the possible resolutions. Each GT
has its own hardware requirements and limitations. Therefore, to use the HDMI 1.4/2.0 Transmitter Subsystem with
different GT devices, calculate the clock frequencies and make sure the targeted device is able to support it. When
using the HDMI 1.4/2.0 Transmitter Subsystem with Xilinx Video PHY Controller IP core, more information can be
found in Video PHY Controller LogiCORE IP Product Guide (PG230)
For example, 1080p60, 12BPC, and 2PPC are used to show how all the clocks are derived.
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Function
= 1/10 data rate
(for data rates < 3.4 Gb/s)
= 1/40 data rate
(for data rates > 3.4 Gb/s)
= TMDS clock
(for data rates < 3.4 Gb/s)
= TMDS clock * 4
(for data rates > 3.4 Gb/s)
= 1/4 of data clock
for 8 bpc pixel
clock = data clock
for 10 bpc pixel
clock = data clock/1.25
for 12 bpc pixel
clock = data clock/1.5
for 16 bpc pixel
clock = data clock/2
for dual pixel video
clock = pixel clock/2
for quad pixel video
clock = pixel clock/4
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Chapter 3:
HDMI Clocking
Freq/Rate
Data rate = 2.97 Gb/s
TMDS clock = 2.97/10 = 297 MHz
Data rate = 5.94 Gb/s
TMDS clock = 5.94/40 = 148.5 MHz
Data rate = 2.97 Gb/s
Data clock = TMDS clock * 1 = 297 MHz
Data rate = 5.94 Gb/s
Data clock = TMDS clock * 4 = 594 MHz
TMDS clock = 148.5 MHz
TMDS clock = 297 MHz
Data clock = 297 MHz
Link clock = 297 MHz/4 = 74.25 MHz
Data clock = 594 MHz
Link clock = 594 MHz/4 = 148.5 MHz
297 MHz/2 = 148.5 MHz for dual pixel
wide interface
297 MHz/4 = 74.25 MHz for quad pixel
wide interface
For more information on how to
choose the correct PLL in the targeted
devices, see the Video PHY Controller
LogiCORE IP Product Guide (PG230)
[Ref 24].
[Ref 24].
Designing with the Subsystem
(1)
Example
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