Xilinx HDMI 1.4 Product Manual page 9

X-Ref Target - Figure 2-3
Figure 2‐3: HDMI TX Subsystem Internal Structure in Native Video Interface Mode
The data width of the video interface is configured in the Vivado IDE by setting the Number
of Pixels Per Clock on Video Interface and the Max Bits Per Component parameters.
The audio interface is a 32-bit AXI4-Stream slave bus, which transports multiple channels of
uncompressed audio data to the subsystem.
The CPU interface is an AXI4-Lite bus interface, which is connected to a MicroBlaze™,
Zynq®-7000 SoC, or Zynq UltraScale™+ MPSoC processor. Multiple submodules are used
to construct the HDMI TX Subsystem and all the submodules which require software access
are connected through an AXI crossbar. Therefore, the MicroBlaze, Zynq-7000 SoC, or Zynq
UltraScale+ MPSoC processor is able to access and control each individual submodules
inside the HDMI TX Subsystem.
The direct register level access to any of the submodules is not supported.
IMPORTANT:
The HDMI TX Subsystem device driver has an abstract layer of API to allow you to
implement certain functions. This AXI4-Lite slave interface supports single beat read and
write data transfers (no burst transfers).
The subsystem converts the video stream and audio stream into an HDMI stream, based on
the selected video format set by the processor core through the CPU interface. The
subsystem then transmits the HDMI stream to the PHY Layer (Video PHY Controller) which
converts the data into electronic signals which are then sent to a HDMI sink through a HDMI
cable.
The subsystem also supports the features described in the following sections.
Audio Clock Regeneration Signals
The transmitter audio peripherals provide a dedicated Audio Clock Regeneration (ACR)
input interface.
The audio clock regeneration architecture is not part of the HDMI TX subsystem. You must
provide an audio clock to the application. This can be achieved by using an internal PLL or
external clock source, depending on the audio clock requirements, audio sample frequency
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017 www.xilinx.com
Chapter 2: Product Specification
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