Xilinx HDMI 1.4 Product Manual page 27

CPU Interface
Table 2-1 shows the AXI4-Lite control interface signals. This interface is an AXI4-Lite
interface and runs at the s_axi_cpu_aclk clock rate. Control of the subsystem is only
supported through the subsystem driver.
The direct register level access to any of the submodules is not supported. Instead, all the
IMPORTANT:
accesses are done through driver APIs.
Table 2‐1: CPU Interface Ports
Name
s_axi_cpu_aresetn
s_axi_cpu_aclk
S_AXI_CPU_IN_awaddr
S_AXI_CPU_IN_awprot
S_AXI_CPU_IN_awvalid
S_AXI_CPU_IN_awready
S_AXI_CPU_IN_wdata
S_AXI_CPU_IN_wstrb
S_AXI_CPU_IN_wvalid
S_AXI_CPU_IN_wready
S_AXI_CPU_IN_bresp
S_AXI_CPU_IN_bvalid
S_AXI_CPU_IN_bready
S_AXI_CPU_IN_araddr
S_AXI_CPU_IN_arprot
S_AXI_CPU_IN_arvalid
S_AXI_CPU_IN_aready
S_AXI_CPU_IN_rdata
S_AXI_CPU_IN_rresp
S_AXI_CPU_IN_rvalid
S_AXI_CPU_IN_rready
HDMI 1.4/2.0 TX Subsystem
PG235 October 4, 2017
Direction Width
Input 1
Input 1
Input 17
Input 3
Input 1
Output 1
Input 32
Input 4
Input 1
Output 1
Output 2
Output 1
Input 1
Input 17
Input 3
Input 1
Output 1
Output 32
Output 2
Output 1
Input 1
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Chapter 2: Product Specification
Description
Reset (Active-Low)
Clock for AXI4-Lite control interface
Write address
Write address protection
Write address valid
Write address ready
Write data
Write data strobe
Write data valid
Write data ready
Write response
Write response valid
Write response ready
Read address
Read address protection
Read address valid
Read address ready
Read data
Read data response
Read data valid
Read data ready
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