16-Bit Data Exchanges; Dxch, Dxchp 32-Bit Data Exchanges - Mitsubishi MELSEC-Q/L Programming Manual

XCH, XCHP, DXCH, DXCHP
[Operation]
Y1F
1 1 1 1 1 1 1 1 1 1
Ignored
b31
0 0 0 0
0 0 0 0
Transfer
0 0 0 0
0 0 0 0
6.4.9 XCH, XCHP

16-bit data exchanges

6.4.9
DXCH, DXCHP 32-bit data exchanges
XCH, XCHP, DXCH, DXCHP
XCH, DXCH
XCHP, DXCHP
, : Head number of the devices where the data to be exchanged is stored (BIN 16/32 bits)
D1 D2
Internal Devices
Setting
Data
Bit Word
D1
D2
Function
XCH
(1) Conducts 16-bit data exchange between
Before execution
After execution
DXCH
(1) Conducts 32-bit data exchange between
Before execution
After execution
270
Y14 Y13
1 1 1 1 0 1 0 1 0 1 0 1 0
20 bits (five digits) data
b20 b19
0 0 0 0 0 0 0 0 1 1 0 1 0
0 0 0 0 0 0 0 0 1 1 0 1 0
0 0 0 0 0 0 0 0 1 1 0 1 0
0 0 0 0 0 0 0 0 1 1 0 1 0
Filled with 0s
Command
Command
J \
R, ZR
Bit
and .
D1 D2
D1
b15 b8 b7
0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1
D1
b15 b8 b7
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
+1, and
D1 D1
+1
D1
b31 b16 b15
1 1 1 1 0 0 0 1 1 1
+1
D1
b31 b16 b15
0 0 0 0 1 1 1 1 1 1
Y0
1 0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0 1 0 1 0
20 bits (five digits)
High
Basic
performance
indicates an instruction symbol of XCH, DXCH.
P
U \G
Word
b0 b15 b8
1 1 1 1 0 0 0 0
b0 b15 b8
0 1 1 1 0 0 0 0
+1, .
D2 D2
+1
D1 D2
b0 b31 b16
0 0 0 0 0 0 0 0 1 1 1
+1
D1 D2
b0 b31 b16
1 1 1 1 1 1 1 1 0 0 0
b0
1 0 1 D11,D10
1 0 1 D13,D12
1 0 1 D15,D14
1 0 1 D17,D16
Process Redundant Universal LCPU
D1 D2
D1 D2
Zn Constants
––
––
D2
b7
b0
1 1 1 1 0 0 0 0
D2
b7 b0
0 0 0 0 0 1 1 1
D2
b15 b0
1 1 1 1 1 1 1
D2
b15 b0
1 1 1 0 0 0 0
Other