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Appendix 1.3
The processing time for the individual instructions are shown in the table on the following pages.
Operation processing time can vary substantially depending on the nature of the sources and destinations of the instructions,
and the values contained in the following tables should therefore be taken as a set of general guidelines to processing times
rather than as being strictly accurate.
When using a file resister (ZR), module access device (Un\G , U3En\G0 to G4095), and link direct device (Jn\ ), add the
processing time shown in Page 744, Appendix 1.3(5) to that of the instruction.
(1) Sequence instructions
Instruction
LD
LDI
AND
ANI
OR
ORI
LDP
LDF
ANDP
ANDF
ORP
ORF
ANB
ORB
MPS
MRD
MPP
INV
MEP
MEF
When not executed
EGP
EGF
When executed
When not changed
When changed
F
OUT
T
C
722
Operation Processing Time of High Performance Model
QCPU/Process CPU/Redundant CPU
Condition (Device)
––
––
––
When not executed
When executed
When not executed
When executed
(OFF OFF)
(ON ON)
(OFF ON)
(ON OFF)
(OFF OFF)
(ON ON)
(OFF ON)
(ON OFF)
When OFF
When
When displayed
ON
Display completed
When not executed
After time up
When
executed
When added
When not executed
After time up
When
executed
When added
Processing Time (µs)
Qn
QnH
0.079
0.034
0.158
0.068
0.079
0.034
0.079
0.034
0.173
0.073
0.158
0.068
0.158
0.068
0.158
0.068
2.8
1.2
162
69.7
126
54
0.63
0.27
0.63
0.27
K
0.63
0.27
D
0.63
0.27
0.63
0.27
0.63
0.27
K
0.63
0.27
D
0.63
0.27
QnPH
QnPRH
0.034
0.034
0.068
0.068
0.034
0.034
0.034
0.034
0.073
0.073
0.068
0.068
0.068
0.068
0.068
0.068
1.2
1.2
69.7
69.7
54
54
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
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