Mitsubishi MELSEC-Q/L Programming Manual page 400

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ECALL, ECALLP
[Operation performed after subroutine program execution]
Before the execution
of subroutine program
D0
0
D1
10
D2
100
Transfer
D3
1000
D4
0
Indefinite
Indefinite
FD0
Indefinite
Indefinite
*1:
Stores the execution result of the subroutine program.
*2:
Replaced by the value of the function device.
(7) The numbers of the devices designated by the arguments in the ECALL(P) instruction should not overlap. If they do
overlap, it will not be possible to obtain accurate calculations.
(8) Up to 16 levels of nesting can be used with the ECALL(P) instruction. However, this 16 levels is the total number of
levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions.
ECALL
FEND
END
(9) Devices which are turned ON within subroutine programs will be latched even if the subroutine program is not executed.
Devices turned ON during the execution of a subroutine program can be turned OFF by the EFCALL(P) instruction.
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Error
code
2410
The specified file does not exist.
2411
The specified file cannot be executed.
The device specified for the argument cannot be secured for the data
4101
size.
The subroutine program of the pointer specified by the ECALL (P)
4210
instruction does not exist.
After the ECALL (P) instruction was executed, the END, FEND,
4211
GOEND, or STOP instruction was executed prior to the RET instruction.
4212
The RET instruction was executed prior to the ECALL (P) instruction.
4213
The 17th nesting level is executed.
398
Immediately after the
execution of ECALL
subroutine program
instruction
D0
0
D1
10
D2
100
D3
1000
0
D4
0
10
FD0
FD0
100
1000
P0
"ABC" P0
ECALL "DEF" P10
RET
Error details
At the time of
execution
D0
0
D0
D1
10
D1
Transfer
D2
100
D2
D3
1000
D3
D4
100 *1
D4
33 *1
1 *1
FD0
100
1000
P10
ECALL "GHI" P20
RET
Q00J/
Q00/
QnH
Q01
After the execution of
RET instruction
33 *2
1 *2
100 *2
1000 *2
100
Indefinite
Indefinite
Indefinite
Indefinite
P20
RET
QnPH QnPRH
QnU
LCPU

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