Mitsubishi MELSEC-Q/L Programming Manual page 274

BXCH, BXCHP
Function
(1) Exchanges 16-bit data of n points from device designated by
.
D2
D1
D1
+1
D1 +2
D1
+(n 2)
D1
+(n 1)
D1
D1 +1
D1
+2
D1 +(n 2)
D1 +(n 1)
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Error
code
The points specified in n exceed those of the corresponding device
4101 specified in or .
D1 D2
The and devices overlap.
D1 D2
Program Example
(1) The following program exchanges 16-bit data for 3 points from D200 for 16-bit data for 3 points from R0 when X1C goes
ON.
[Ladder Mode]
[Operation]
b15 b8 b7
D200 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1
D201 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D202 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
b15 b8 b7
D200 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
D201 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D202 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
272
b15 b8 b7 b0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b15 b8 b7 b0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Error details
[List Mode]
Step
b0 b15
R0
R1
R2
b0 b15
R0
R1
R2
and 16-bit data of n points from device designated by
D1
b15
D2
0 0 1 1 0 0
D2
+1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
D2
+2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
n
D2
+(n 2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D2
+(n 1) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
b15
D2
0 0 0 0 1 1
D2
+1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D2
+2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
n
D2
+(n 2) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
D2
+(n 1) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Q00J/
Q00/ QnH
Q01
Device
Instruction
b8 b7 b0
0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
b8 b7 b0
0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
b8 b7 b0
1 1 0 0 1 1 0 0 1 1
n
b8 b7 b0
1 1 0 0 0 0 1 1 1 1
n
QnPH QnPRH QnU LCPU