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Appendix 1.2
The processing time for the individual instructions are shown in the table on the following pages.
Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions,
and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time
rather than as being strictly accurate.
When using a file resister (ZR), module access device (Un\G , U3En\G0 to G511), and link direct device (Jn\ ), add the
processing time shown in Page 721, Appendix 1.2(6) to that of the instruction.
(1) Sequence instructions
Instruction
LD
LDI
AND
ANI
OR
ORI
LDP
LDF
ANDP
ANDF
ORP
ORF
ANB
ORB
MPS
MRD
MPP
INV
MEP
MEF
When not
executed
EGP
executed
When not
executed
EGF
executed
When not
changed
Y
changed
When not
OUT
changed
D0.0
changed
F
When
Operation Processing Time of Basic Model QCPU
Condition (Device)
X0
D0.0
X0
D0.0
––
When not executed
When executed
When not executed
When executed
(OFF OFF)
(ON ON)
When
(OFF ON)
(ON OFF)
(OFF OFF)
(ON ON)
When
(OFF ON)
(ON OFF)
(OFF OFF)
(ON ON)
When
(OFF ON)
(ON OFF)
(OFF OFF)
(ON ON)
When
(OFF ON)
(ON OFF)
When OFF
When displayed
ON
Display completed
Processing Time (µs)
Q00JCPU
Q00CPU
0.20
0.16
0.30
0.24
0.30
0.24
0.20
0.16
0.20
0.16
0.30
0.24
0.20
0.16
17
9.5
18
14
0.20
0.16
0.20
0.16
0.40
0.32
0.40
0.32
24
20
260
210
205
165
3
2
3
A
Q01CPU
5
0.10
6
0.15
7
0.15
8
0.10
0.10
0.15
0.10
9.4
14
0.10
0.10
0.20
0.20
19
200
155
707
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