Mitsubishi MELSEC-Q/L Programming Manual page 700

D.DDWR, DP.DDWR
Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Error
code
Specified another CPU is incorrect. Or the multiple CPU high-speed
transmission dedicated instruction is disabled.
• The reserved CPU has been specified.
• A CPU that is not mounted has been specified.
• Another CPU start I/O number divided by 16n is not within the range
from 3E0 to 3E3 .
H H
4350
• The instruction was executed when the module is set to "Do not use
multiple CPU high speed transmission".
• The instruction was executed with the CPU module that cannot use
this instruction.
• The host CPU has been specified.
• The CPU where the instruction cannot be executed has been
specified.
4351 Another CPU does not support this instruction.
4352 The number of devices is incorrect.
4353 The device that cannot be used for the instruction has been specified.
A device has been specified by the character string that cannot be
4354
used.
4355
The number of write points, ( +1), is other than 0 to 100.
In any of the following cases, the instruction is completed abnormally, and an error code is stored into a device specified
at completion status storage device ( +0).
Error
code
The request of the instruction to the target CPU is more than the
0010
acceptable value (no empty block exists in the multiple CPU high speed
H
transmission area).
A device of another CPU specified in
1001
H
is outside the device range.
The response of the instruction from another CPU cannot be returned
1003
(no empty block exists in the multiple CPU high speed transmission
H
area).
1080
The number of write points set with the D(P).DDWR instruction is 0.
H
Program Example
(1) This program stores data by 10 words starting from D0 in host CPU into W10 or later in CPU No.2 when X0 turns on.
[Ladder Mode]
698
Error details
S1
S1
Error details
cannot be used for the CPU, or
D1
[List Mode]
Q00J/
Q00/ QnH QnPH QnPRH
Q01
–– –– –– ––
–– –– –– ––
–– –– –– ––
–– –– –– ––
–– –– –– ––
–– –– –– ––
Q00J/
Q00/ QnH QnPH QnPRH
Q01
–– –– –– ––
–– –– –– ––
–– –– –– ––
–– –– –– ––
QnU LCPU
––
––
––
––
––
––
QnU LCPU
––
––
––
––