Mitsubishi MELSEC-Q/L Programming Manual page 677

Writing data to CPU shared memory can be performed using the intelligent function module device.
For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals)
or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).
Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Error
code
When the head I/O number (n1) of the host CPU is other than that of
2107
the host CPU.
No CPU module is installed at the position specified for the head I/O
2110
number of the CPU module.
4002 When the specified instruction is improper.
4003 When the number of devices specified is incorrect.
4004 When an Unavailable device is specified.
When the head I/O number (n1) of the host CPU is other than 3E0
4100
3E1 /3E2 /3E3 .
H H H
When the host CPU operation information area, system area, or host
CPU refresh area is specified to the CPU shared memory address (n2)
of the write destination.
When the number of write points (n4) is outside the specified range of
the setting data.
When the head of the CPU shared memory address (n2) of the write
4101
destination host CPU exceeds the CPU shared memory address range.
When the CPU shared memory address (n2) + the number of write
points (n4) of the write destination host CPU exceeds the CPU shared
memory address range.
When the head number of the devices (n3) where the data to be written
is stored + the number of write points (n4) exceeds the device range.
When the host CPU operation information area, system area, or host
4111 CPU refresh area is specified to the CPU shared memory address (n2)
of the write destination.
When the head I/O number (n1) of the host CPU is other than that of
4112
the host CPU.
Program Example
(1) The following program stores 10 points of data from D0 into address 800
when X0 is turned ON.
[Ladder Mode]
Error details
[List Mode]
Step
Q00J/
Q00/ QnH QnPH QnPRH
Q01
––
/
H
––
––
––
of the CPU shared memory of CPU No. 1
H
Instruction Device
S.TO, SP.TO
QnU LCPU
–– –– ––
–– ––
–– ––
–– ––
–– ––
–– ––
–– –– ––
–– ––
–– –– ––
–– –– ––
675
9
2
3
4
4
6
7
8