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E
Encoding from 256 to 8 bits . . . . . . . . . . . . . . . . . . . 359
Error display and annunciator reset . . . . . . . . . . . . . 437
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Expansion clock data addition operation . . . . . . . . . 591
Expansion clock data subtraction operation . . . . . . . 594
Expansion Clock Instructions . . . . . . . . . . . . . . . . . . 589
Exponent operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Exponent operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Exponentiation operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Exponentiation operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Extracting character string data from the left . . . . . . 485
Extracting character string data from the right . . . . . 485
F
File register direct 1-byte write . . . . . . . . . . . . . . . . . 609
File register switching instructions . . . . . . . . . . . . . . 566
File setting for comments . . . . . . . . . . . . . . . . . . . . . 569
File setting for file register . . . . . . . . . . . . . . . . . . . . . 567
Fixed cycle pulse output . . . . . . . . . . . . . . . . . . . . . . 300
Floating-point data comparisons
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Floating-point data comparisons
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Floating-point data to BCD . . . . . . . . . . . . . . . . . . . . 496
Floating-point data transfer (Double precision) . . . . . 258
Floating-point data transfer (Single precision) . . . . . 257
Floating-point sign inversion (Double precision) . . . . 249
Floating-point sign inversion (Single precision). . . . . 248
FOR to NEXT instruction loop. . . . . . . . . . . . . . . . . . 383
Forced end of FOR to NEXT instruction loop . . . . . . 385
From BCD format data to floating-point data . . . . . . 498
G
GX Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
GX Works2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
H
High Performance model QCPU . . . . . . . . . . . . . . . . . 23
High-speed block transfer of file register. . . . . . . . . . 658
High-speed retentive timer . . . . . . . . . . . . . . . . . . . . 141
High-speed timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
How to Read Instruction Tables . . . . . . . . . . . . . . . . . 27
I
I/O refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
I/O Refresh Instructions . . . . . . . . . . . . . . . . . . . . . . 285
Identical 16-bit data block transfer . . . . . . . . . . . . . . 266
Identical 32-bit data block transfer . . . . . . . . . . . . . . 268
Index modification of entire ladder . . . . . . . . . . . . . . 413
Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Indexing with 16-bit index registers. . . . . . . . . . . . . . . 91
Indexing with 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Indirect address read operations . . . . . . . . . . . . . . . 611
Indirect Specification . . . . . . . . . . . . . . . . . . . . . . . . . 100
Insertion of character string . . . . . . . . . . . . . . . . . . . 492
836
Insertion of data in data tables . . . . . . . . . . . . . . . . . 423
Instructions whose designation format has been
changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Intelligent function module device . . . . . . . . . . . . . . . 23
Interrupt disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Interrupt program mask . . . . . . . . . . . . . . . . . . . . . . 278
J
Jump to END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
L
L series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Ladder block parallel connection . . . . . . . . . . . . . . . 131
Ladder block series connection . . . . . . . . . . . . . . . . 131
LCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Leading edge output . . . . . . . . . . . . . . . . . . . . . . . . 152
Left rotation of 16-bit data . . . . . . . . . . . . . . . . . . . . 333
Left rotation of 32-bit data . . . . . . . . . . . . . . . . . . . . 337
Linking character strings . . . . . . . . . . . . . . . . . . . . . 225
Linking of random data. . . . . . . . . . . . . . . . . . . . . . . 365
List of arithmetic operation instructions . . . . . . . . . . . 39
List of association instructions . . . . . . . . . . . . . . . . . . 30
List of bit processing instructions . . . . . . . . . . . . . . . . 56
List of buffer memory access instructions . . . . . . . . . 62
List of character string processing instructions . . . . . 63
List of clock instructions . . . . . . . . . . . . . . . . . . . . . . . 72
List of comparison operation instructions. . . . . . . . . . 33
List of contact instructions . . . . . . . . . . . . . . . . . . . . . 29
List of data control instructions. . . . . . . . . . . . . . . . . . 70
List of data conversion instructions . . . . . . . . . . . . . . 44
List of data processing instructions . . . . . . . . . . . . . . 56
List of data transfer instructions . . . . . . . . . . . . . . . . . 47
List of debugging and failure diagnosis instructions. . 63
List of display instructions . . . . . . . . . . . . . . . . . . . . . 62
List of expansion clock instructions . . . . . . . . . . . . . . 75
List of I/O refresh instructions . . . . . . . . . . . . . . . . . . 49
List of instructions for Multiple CPU
high-speed transmission dedicated . . . . . . . . . . . . . . 81
List of instructions for Network refresh. . . . . . . . . . . . 79
List of instructions for reading from
the CPU shared memory of another CPU . . . . . . . . . 80
List of instructions for reading/writing routing
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
List of instructions for Redundant system
(For Redundant CPU) . . . . . . . . . . . . . . . . . . . . . . . . 81
List of instructions for writing to
the CPU shared memory of host CPU . . . . . . . . . . . . 80
List of logical operation instructions . . . . . . . . . . . . . . 51
List of master control instructions. . . . . . . . . . . . . . . . 32
List of other convenient instructions. . . . . . . . . . . . . . 50
List of other instructions . . . . . . . . . . . . . . . . . . . . . 32,76
List of output instructions . . . . . . . . . . . . . . . . . . . . . . 31
List of program branch instructions . . . . . . . . . . . . . . 49
List of program control instructions . . . . . . . . . . . . . . 76
List of program execution control instructions . . . . . . 49
List of rotation instructions . . . . . . . . . . . . . . . . . . . . . 53
List of shift instructions. . . . . . . . . . . . . . . . . . . . . . 31,54
List of special function instructions. . . . . . . . . . . . . . . 67
List of structure creation instructions . . . . . . . . . . . . . 59
List of switching instructions. . . . . . . . . . . . . . . . . . . . 72
List of table operation instructions . . . . . . . . . . . . . . . 61
List of termination instructions . . . . . . . . . . . . . . . . . . 32
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