Omron CS1G/H-CPUxx-EV1 Programming Manual page 224

Interrupt Tasks
Related Auxiliary Area Flags/Words
Name
Interrupt Task Error A40213
Flag
Interrupt Task Error, A426
Task Number
Disabling Interrupts
Data Concurrency
between Cyclic and
Interrupt Tasks
188
Address
Turns ON if an interrupt task executes for more than 10 ms during
C200H Special I/O Unit or SYSMAC BUS Remote I/O refresh, but the
CPU Unit will continue running. The ERR/ALM LED will light on the
front panel (CS Series only).
Turns ON if you try to refresh a Special I/O Unit with an IORF instruc-
tion from an interrupt task while that Unit is being refreshed by cyclic
I/O refresh.
Contains the interrupt task number or the number of the Special I/O
Unit being refreshed.
(Bit 15 will be OFF when execution of an interrupt task requires 10 ms
or longer and ON when duplicated Special I/O Unit refreshing has
occurred.)
Processing will be interrupted and the interrupt task will be executed in the fol-
lowing instances.
• While an instruction is being executed
• During Basic I/O Unit, CPU Bus Unit, Inner Board (CS Series only), or
SYSMAC BUS remote I/O (CS Series only) refreshing
• During HOST LINK servicing
Data may not be concurrent if a cyclic (including extra cyclic tasks) and an
interrupt task are reading and writing the same I/O memory addresses. Use
the following procedure to disable interrupts during memory access by cyclic
task instructions.
• Immediately prior to reading or writing by a cyclic task instruction, use a
DI (DISABLE INTERRUPT) instruction to disable execution of interrupt
tasks.
• Use an EI (ENABLE INTERRUPT) instruction immediately after process-
ing in order to enable interrupt task execution.
Reading and writing I/O
memory common to
interrupt tasks.
Processing with interrupt task
execution enabled
Problems may occur with data concurrency even if DI(693) and EI(694) are
used to disable interrupt tasks during execution of an instruction that requires
response reception and processing (such as a network instruction or serial
communications instruction).
Note With the CS1-H, CJ1-H, CJ1M, or CS1D CPU Unit, execution of the BIT
COUNTER (BCNT), BLOCK SET (BSET), and BLOCK TRANSFER (XFER)
Description
Cyclic task
Section 4-3
Disabled
Interrupt task
Enabled
Interrupt task