Block And One Data Burst Mode - Samsung S3C2501X User Manual

GDMA CONTROLLER
9.6.3 BLOCK AND ONE DATA BURST MODE (DCON[3:1] = 001, [4] = 1, [5] = 0)
xGDMA_Req and xGDMA_Ack signals are active high.
GDMA transfers data from single xGDMA_Req signal till GDMA Transfer Count Register (DTCR) consumes to 0.
HCLK
xGDMA_Req
xGDMA_Ack
Address
Data
NOTE: ' a ' is in the block mode, GDMA starts to operate with first xGDMA_Req signal. So in the ideal case,
GDMA does not care the number of xGDMA_Req signal pulse. But I recommand that xGDMA_Req
siganl is deasserted when xGDMA_Ack signal is active state.
9-22
Recommand
deasserted time
Programmable by
DCON[16:13]
SA0 DA0
SD0
Figure 9-13. Block and One Data Burst Mode Timing
a
Programmable by
DD0
DCON[16:13]
SA1 DA1
SD1
S3C2501X
DD1