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INSTRUCTION SET
3.19 THUMB INSTRUCTION SET FORMAT
The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are
reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The
thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the
ARM9TDMI core.
As the Thumb instructions are compressed ARM instructions, the Thumb instructions have the 16-bit format
instructions and have some restrictions. The restrictions by 16-bit format is fully notified for using the Thumb
instructions.
3.19.1 FORMAT SUMMARY
The THUMB instruction set formats are shown in the following figure.
15 14 13 12 11 10
1
0
0
0
2
0
0
0
3
0
0
1
4
0
1
0
5
0
1
0
6
0
1
0
7
0
1
0
8
0
1
0
9
0
1
1
10
1
0
0
11
1
0
0
12
1
0
1
13
1
0
1
14
1
0
1
15
1
1
0
16
1
1
0
17
1
1
0
18
1
1
1
19
1
1
1
1
1
1
15 14 13 12 11 10
3-64
9
8
7
Op
Offset5
1
1
I
Op
Rn/offset3
Op
Rd
0
0
0
Op
0
0
1
Op
H1 H2
0
1
Rd
1
L
B
0
Ro
1
H
S
1
Ro
B
L
Offset5
0
L
Offset5
1
L
Rd
0 SP
Rd
1
0
0
0
0
S
1
L
1
0
R
0
L
Rb
1
Cond
1
1
1
1
1
0
0
1
1
H
9
8
7
Figure 3-29. THUMB Instruction Set Formats
6
5
4
3
2
1
Rs
Rd
Rs
Rd
Offset8
Rs
Rd
Rs/Hs
Rd/Hd
Word8
Rb
Rd
Rb
Rd
Rb
Rd
Rb
Rd
Word8
Word8
SWord7
Rlist
Rlist
Softset8
Value8
Offset11
Offset
6
5
4
3
2
1
0
Move Shifted register
Add/subtract
Move/compare/add/
subtract immediate
ALU operations
Hi regiter operations
/branch exchange
PC-relative load
Load/store with register
offset
Load/store sign-extended
byte/halfword
Load/store with immediate
offset
Load/store halfword
SP-relative load/store
Load address
Add offset to stack pointer
Push/pop register
Multiple load/store
Conditional branch
Software interrupt
Unconditional branch
Long branch with link
0
S3C2501X
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