Samsung S3C2501X User Manual page 309

ETHERNET CONTROLLER
7.4.1.8 BDMA/MAC Transmit Interrupt Status Register
Registers Address
BMTXSTATA 0xF00A0020
BMTXSTATB 0xF00C0020
Bit Number
[0] Excessive collision (ExColl) This bit is set when collision occurred 16 times consecutively. In
[1] Underflow
[2] Deferral Error (DeferErr)
[3] No carrier (NoCarr)
[4] Late collision (LateColl)
[5] Transmit parity error
(TxParErr)
[6] Tx Completion (TxComp)
[15:7] Reserved
[16] Tx complete to send control
frame (TxCFcomp)
[17] BDMA Tx not owner
(BTxNO)
[18] BDMA TxBUFF empty
(BTxEmpty)
[31:19] Reserved
7-20
Table 7-11. BMTXSTAT Register
R/W
R/W
R/W
Bit Name
this case, the frame transmission is aborted. If this bit is the
cause of the interrupt, MTxEn/BTxEn/MReset bit should be
cleared for the re-transmission of the current frame.
This bit is set if the MAC TxFIFO becomes empty during the
frame transmission.
This bit is set when MAC doesn't run the transmission process
from TX_EN falling to 6,071 nibble times or 24,284 bit times.
This bit is set if no carrier sense is detected during the
transmission frame.
This bit is set if a collision occurs after 512 bit times
(or 64 byte times).
This bit is set if a parity error is detected in the MAC TxFIFO.
This bit is set when the transmission always is completed with
normal or abnormal status.
Not applicable.
This bit is set each time the MAC sends a complete control
frame.
This bit is set when BDMA is not owner and the transmission
process is stop.
This bit is set when the BDMA TxBUFF is empty.
Not applicable.
Description
BDMA/MAC Tx Interrupt Status Register
BDMA/MAC Tx Interrupt Status Register
Description
S3C2501X
Reset Value
0x00000000
0x00000000