Cpsr Flags; Instruction Cycle Times - Samsung S3C2501X User Manual

INSTRUCTION SET S3C2501X

3.8.2 CPSR FLAGS

Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set
correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero).
Both the C and V flags are set to meaningless values.

3.8.3 INSTRUCTION CYCLE TIMES

MULL takes 1S + (m+1)I and MLAL 1S + (m+2)I cycles to execute, where m is the number of 8 bit multiplier
array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified
by Rs.
Its possible values are as follows:
For Signed Instructions SMULL, SMLAL:
— If bits [31:8] of the multiplier operand are all zero or all one.
— If bits [31:16] of the multiplier operand are all zero or all one.
— If bits [31:24] of the multiplier operand are all zero or all one.
— In all other cases.
For Unsigned Instructions UMULL, UMLAL:
— If bits [31:8] of the multiplier operand are all zero.
— If bits [31:16] of the multiplier operand are all zero.
— If bits [31:24] of the multiplier operand are all zero.
— In all other cases.
S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively.
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