Format 16: Conditional Branch; Operation - Samsung S3C2501X User Manual

S3C2501X

3.35 FORMAT 16: CONDITIONAL BRANCH

15 14 13
1 1 0

3.35.1 OPERATION

The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition
codes. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4
bytes) ahead of the current instruction.
The THUMB assembler syntax is shown in the following table.
Code THUMB
Assembler
0000 BEQ label
0001 BNE label
0010 BCS label
0011 BCC label
0100 BMI label
0101 BPL label
0110 BVS label
0111 BVC label
1000 BHI label
1001 BLS label
1010 BGE label
12 11
1 Cond
[7:0] 8-bit Signed Immediate
[11:8] Condition
Figure 3-45. Format 16
Table 3-23. The Conditional Branch Instructions
ARM Equivalent
BEQ label Branch if Z set (equal)
BNE label Branch if Z clear (not equal)
BCS label Branch if C set (unsigned higher or same)
BCC label Branch if C clear (unsigned lower)
BMI label Branch if N set (negative)
BPL label Branch if N clear (positive or zero)
BVS label Branch if V set (overflow)
BVC label Branch if V clear (no overflow)
BHI label Branch if C set and Z clear (unsigned higher)
BLS label Branch if C clear or Z set (unsigned lower or same)
BGE label Branch if N set and V set, or N clear and V clear
(greater or equal)
8 7
INSTRUCTION SET
SOffset 8
Action
0
3-91