I 2 C Control Status Register - Samsung S3C2501X User Manual

32-bit risc microprocessor
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S3C2501X
31
[0] Buffer Flag (BF)
0 = Automatically cleared when the IICBUF register is written or read. To manually
clear the BF, write 0.
1 = Automatically set when the buffer is empty in transmit mode or when the buffer
is full in receive mode.
[1] Interrupt enable (IEN)
0 = Disable
1 = Enable; an interrupt is generated if the BF bit is 1.
[2] Last received bit (LRB)
Use this read-only status bit to check for ACK signals from the receiver (slave), or
to monitor SDA operation of SDA when writing 11 to IICCON [5:4] for repeated
starts.
0 = The most recent SDA is low. (ACK is received)
1 = The most recent SDA is high. (ACK not received)
[3] Acknow enable (ACK)
Controls generation of an ACK signal in receive mode.
0 = Do not generate an ACK at 9th SCL (No more received data is required from
the slave)
1 = Generate an ACK signal at 9th SCL.
[5:4] COND 1 and COND 0
Generate a control such as start or stop.
00 = No effect.
01 = Generate start condition. (BF bit should be set simultaneously)
10 = Generate stop condition.
11 = SCL will be released to high level to generate repeated start condition.
[6] Bus busy (BUSY)
Data transmission is in progress on the IIC-bus.
0 = Bus is currently not in use. (not busy)
1 = Bus is in use. (busy)
[7] Reset
0 = Normal
1 = Reset the IIC controller.
[31:8] Reserved
Reserved
(ACK bit should be set simultaneously)
Figure 6-6. I
2
C Control Status Register
2
I
C CONTROLLER
8 7
6 5 4 3 2 1
R
B
C
C
A
L
I
E
U
O
O
C
R
E
S
S
N
N
K
B
N
E
Y
D
D
T
1
0
0
B
F
6-9

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