Core Pll Control Register - Samsung S3C2501X User Manual

SYSTEM CONFIGURATION
4.8.7 CORE PLL CONTROL REGISTER (CPLLCON)
If you want to use this register, you should set CPLLREN in SYSCFG[31] to "1". This register doesn't work with
CPLLREN set to "0".
Register Address
CPLLCON 0xF000001C
CPLLCON Bit
Reserved [31:12]
S [17:16]
Reserved [15:14]
P [13:8]
M [7:0]
Output clock frequency is determined by following formula.
Fout = Fin × (M+8) / ((P+2) × (2^S))
If Fin = 10MHz, P = 3, M = 158 (0x9E), and S = 1, Fout is 166 MHz.
FCLK signal of ARM940T core is connected to Fout, 166MHz clock. But, BCLK signal of ARM940T and system
bus clock is connect to Fout / 2, 66 MHz clock.
4-22
R/W
R/W
Scaler
Pre divider
Main divider
Description

Core PLL control register

Description
S3C2501X
Reset Value
0x0001039E
Initial State
0x0
0x1
0x0
0x3
0x9E