S3C2501X
5.6.4 TIMING DIAGRAM
HCLKO
tRCSd
nRCS
tnOEd
nOE
tADDRd
ADDR
DATA
tACC
tDATAd
TACC = 0x8 (8 cycles)
TCOH = 0x0 (0 cycle)
Figure 5-14. Read Timing Diagram 1
Addr
Data
TCOS = 0x0 (0 cycle)
TACS = 0x0 (0 cycle)
MEMORY CONTROLLER
tRCSh
tnOEh
tADDRh
tDATAh
D ata Fetch
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