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S3C2501X
3.16.2 TRANSFERS TO R15
When a coprocessor register transfer to ARM9TDMI has R15 as the destination, bits 31, 30, 29 and 28 of the
transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are
ignored, and the PC and other CPSR bits are unaffected by the transfer.
3.16.3 TRANSFERS FROM R15
A coprocessor register transfer from ARM9TDMI with R15 as the source register will store the PC+ 12.
3.16.4 INSTRUCTION CYCLE TIMES
MRC instructions take 1S + (b+1)I +1C incremental cycles to execute, where S, I and C are defined as sequential
(S-cycle), internal (I-cycle), and coprocessor register transfer (C-cycle), respectively. MCR instructions take 1S +
bI +1C incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop.
3.16.5 ASSEMBLER SYNTAX
<MCR|MRC>{cond} p#,<expression1>,Rd,cn,cm{,<expression2>}
MRC
MCR
{cond}
p#
<expression1>
Rd
cn and cm
<expression2>
Examples
MRC
MCR
MRCEQ
Move from coprocessor to ARM9TDMI register (L = 1)
Move from ARM9TDMI register to coprocessor (L = 0)
Two character condition mnemonic. See Table 3-2.
The unique number of the required coprocessor
Evaluated to a constant and placed in the CP Opc field
An expression evaluating to a valid ARM9TDMI register number
Expressions evaluating to the valid coprocessor register numbers CRn and CRm
respectively
Where present is evaluated to a constant and placed in the CP field
p2,5,R3,c5,c6
p6,0,R4,c5,c6
p3,9,R3,c5,c6,2
; Request coproc 2 to perform operation 5
; on c5 and c6, and transfer the (single
; 32-bit word) result back to R3.
; Request coproc 6 to perform operation 0
; on R4 and place the result in c6.
; Conditionally request coproc 3 to
; perform operation 9 (type 2) on c5 and
; c6, and transfer the result back to R3.
INSTRUCTION SET
3-57
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