Console Uart Control Registers - Samsung S3C2501X User Manual

SERIAL I/O (CONSOLE UART)

10.3.1 CONSOLE UART CONTROL REGISTERS

Register Address
CUCON 0xF0060000
Bit Number
[1:0] Transmit mode
(TMODE)
[3:2] Receive mode (RMODE) This two-bit value determine which function is currently able to read
[4] Send Break (SBR)
[5] Serial Clock Select
(SCSEL)
[6] Reserved
[7] Loop-back mode
(LOOPB)
[10:8] Parity mode (PMD)
[11] Number of Stop bits
(STB)
10-4
Table 10-2. CUCON Registers
R/W
R/W Console UART control register
Table 10-3. Console UART Control Register Description
Bit Name
This two-bit value determine which function is currently able to write
TX data to the Console UART transmit data register, CUTXBUF.
00 = Disable TX mode
10 = Reserved
RX data from the Console UART receive data register, CURXBUF.
NOTE:
00 = Disable RX mode
10 = Reserved
Set this bit to one to cause the Console UART to send a break. If
this bit value is zero, a break does not send. A break is defined as a
continuous Low level signal on the transmit data output with the
duration of more than one frame transmission time.
This select bit specifies the clock source
0 = Internal (PCLK2)
1 = External (EXT_UCLK)
Reserved
Setting this bit causes the Console UART to enter Loop-back mode.
In Loop-back mode, the transmit data output, CUTXD, keeps '1' and
the transmit data register, CUTXBUF, is internally connected to the
receive data register, CURXBUF.
NOTE: This mode is provided for test purposes only. For normal
The 3-bit parity mode value specifies how parity generation and
checking are performed during Console UART transmit and receive
operations:
0xx = No parity
110 = Parity is forced/checked as a '1'
111 = Parity forced/checked as a '0'
This bit specifies how many stop bits are used to signal end-of-
frame (EOF):
0 = One stop bit per frame
Description
Description
01 = CPU request
Changing these bits (TMODE, RMODE) while
transmitting/receiving cause abnormal UART operation. To
prevent Tx/Rx data from being lost, changing these bits while
transmitting/receiving is strictly prohibited.
operation, this bit should always be '0'.
100 = Odd parity
1 = Two stop bit per frame
Size Reset Value
W
11 = Reserved
01 = CPU request
11 = Reserved
101 = Even parity
S3C2501X
0x00000000