Timing For Transmission With Collision In Preamble - Samsung S3C2501X User Manual

ETHERNET CONTROLLER S3C2501X
Tx_clk
Tx_en
P1 P2 P3 P4 P5 P6 P7 P8 J1 J2 J3 J4
TxD [3:0]
Crs
Col
Figure 7-8. Timing for Transmission with Collision in Preamble
7.5.1.3.2. BDMA/MAC Interface Operation for Transmission
The BDI transmit operation is a simple FIFO mechanism. The BDMA engine stores data to be transmitted, and
the transmission state machine empties it when the MAC successfully acquires the net.
Note that the two time domains intersect at the FIFO controller. The writing and reading of data is asynchronous
and on different clocks. Reading is driven by either a 25MHz or a 2.5MHz TX_CLK. Writing is driven by system
clock, which is asynchronous to TX_CLK.
After a reset, the MTxFIFO is empty. To enable the transmission, the system must set the transmit enable bit in
the MACTXCON register. In addition, eight bytes of data must be present in the MTxFIFO. The BDMA engine
can start stuffing data into the MTxFIFO and then enable the transmit bit. (or it can enable the transmit bit first
and then start stuffing data into the MTxFIFO) The transmitting operation can only start if both of these
conditions are met.
7.5.1.4. Receiving a Frame
The receiver block, when enabled, constantly monitors a data stream coming either from the MII or, if in loop-
back mode, from the transmitter block. The MII supplies from zero to seven bytes of preamble, followed by the
start frame delimiter (SFD). The receiver block checks that the first nibbles received are preamble, and then
looks for the SFD (10101011) in the first 8-byte. If it does not detect the SFD by then, it treats the frame as a
fragment and discards it.
The first nibble of destination address follows the SFD, LSB first. When it has received a byte, the receiver block
generates parity, stores the byte with its parity in the MRxFIFO. It combines subsequent nibbles into bytes and
stores them in the FIFO.
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