Table of Contents
Advertisement
S3C2501X
7
ETHERNET CONTROLLER
7.1 OVERVIEW
The S3C2501X has two Ethernet controllers that operate at either 100M-bit or 10M-bit per second in half-duplex
or full-duplex mode. In half-duplex mode, the IEEE 802.3 carrier sense multiple access with collision detection
(CSMA/CD) protocol is supported. In full-duplex mode, the IEEE 802.3 MAC control layer is also supported,
including the pause operation for flow control.
The two Ethernet controllers support both the media independent interface (MII) and the buffered DMA interface
(BDI). The MAC layer consists of a receiver and a transmitter blocks, a flow control block, a content addressable
memory(CAM) for storing network addresses, a number of commands, status, and error counter registers.
The MII supplies the transmission and reception clocks of 25MHz for 100M-bps operation, 2.5 MHz for the 10M-
bps speed or 1MHz for (the 1M-bps for) Home PNA. The MII conforms to the ISO/IEC 802-3 standards.
BDMA Tx
Buffer
Controller
32
Bus Arbiter/
Controller
S
Y
S
32
T
BDMA Rx
E
Buffer
M
Controller
B
U
32
S
BDMA
BDMA Tx
Buffer
32
(64 words)
B
BDMA Rx
D
Buffer
I
(64 words)
32
CAM
Contents
32
Memory
(32-words)
BDMA
Control
and Satus
register
Figure 7-1. Ethernet Diagram
MAC
MAC
TxFIFO
(80x9)
Backoff
Preamble/
and
SFD/CRC/
Intergap
PAD/JAM
timer
Generator
MAC
RxFIFO
(16x10)
CAM
CRC
Checker
Checker
(32x32)
Flow Control
MAC Control and
Status
ETHERNET CONTROLLER
PHYSICAL
LAYER
M
I
I
/
10
M
b
p
s
7
Preamble/
-
SFD
W
Detector
i
r
e
Station
Manager
M
D
I
7-1
Advertisement
Table of Contents
