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GDMA CONTROLLER
9.6.1 SINGLE AND ONE DATA BURST MODE (DCON[3:1] = 001, [4] = 0, [5] = 0)
xGDMA_Req and xGDMA_Ack signals are active high.
HCLK
xGDMA_Req
xGDMA_Ack
Address
Data
NOTES:
1.
In this region, GDMA operation is independent of the number of xGDMA_Req signal pulse.
For example, although xGDMA_Req signal pulses 3 times in the '
data only one time from source address to destination address. Current xGDMA_Req signal
is idle state (deasserted) when xGDMA_Ack siganl is idle state (high).
Otherwise, GDMA recognizes current xGDMA_Req signal as next one and transfers next data.
I recommand that xGDMA_Req signal is deasserted when xGDMA_Ack signal is active.
2.
'
b
3.
'
c
9-20
a
b
' is minimum two cycles.
' can be programmed by setting DCON[16:13]. '
Figure 9-11. Single and One Data Burst Mode Timing
Recommand
deasserted time
c
source
dest.
addr
addr
source
dest.
data
data
' can be between 1 and 16 cycles.
c
' region, GDMA transfers
a
S3C2501X
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