The Mii Station Manager - Samsung S3C2501X User Manual

32-bit risc microprocessor
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S3C2501X

7.5.2 THE MII STATION MANAGER

The MDIO (management data input/output) signal line is the transmission and reception path for control/status
information for the station management entity, STA. The STA controls and reads the current operating status of
the PHY layer. The speed of transmit and receive operations is determined by the management data clock,
MDC.
The frame structure of the STA that writes command to control registers, or which reads the status register of a
PHY device, is shown Table 7-30. The PHY address is defined as the identification (ID) value of the various PHY
devices that may be connected to a single MAC. Register addresses can contain the ID value for up to 32 types
of PHY registers.
Turn-around bits are used to regulate the turn-around time of the transmit/receive direction between the STA and
a PHY device. So that the STA can read the set value of a PHY device register, it must transmit the frame data,
up to a specific register address, to the PHY device. During the write time (which is an undirected transmission),
the STA transmits a stream of turn-around bits. As a result, by transmitting a write or read message to a PHY
device through the MDIO, the STA can issue a request to set the operation or to read the operation status.
As its response this message, the PHY device resets itself, sets loop-back mode, selects active/non-active auto-
negotiation process, separates the PHY and MII electrically, and determines whether or not to activate the
collision detection process.
When it receives a read command, the PHY reports the type of PHY device such as 100 base-T4, FDX 100
base-X, HDX 100Base-X, 10M-b/s FDX, or 10M-b/s HDX.
Preamble
Write
11111111
(Command)
(32 bits)
Read (Status) 11111111
(32 bits)
Table 7-30. STA Frame Structure Description
Start of
Operation
Frame
Code
01
01 (write)
01
10 (read)
Direction: STA to PHY
PHY
Register
Address
Address
5 bits
5 bits
5 bits
5 bits
ETHERNET CONTROLLER
Turnaround
Data
10 (2 bits)
16 bits
(register
value)
Z0
16 bits
(register
value)
Direction: PHY to STA
Idle
Z
Z
7-45

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