Gdma Interrupt Pending Register - Samsung S3C2501X User Manual

S3C2501X

9.3.6 GDMA INTERRUPT PENDING REGISTER

The GDMA interrupt pending register (DIPR) indicates the pending state of GDMA interrupt by the pending bit [0]
of the DIPR register. The DIPR[0] is active high. The DIPR[0] can be asserted after the GDMA operation
completes successfully when the Interrupt Enable field of DCON[12] is "1". Once the GDMA interrupt service
routine is called, the DIPR[0] should be de-asserted by writing "1" on DIPR[0] in the beginning of the GDMA
interrupt service routine.
Registers Address
DIPR0 0xF0050014
DIPR1 0xF0050034
DIPR2 0xF0050054
DIPR3 0xF0050074
DIPR4 0xF0050094
DIPR5 0xF00500B4
31
Table 9-8. DIPR0/1/2/3 Registers
R/W
R/WC GDMA channel 0 interrupt pending register
R/WC GDMA channel 1 interrupt pending register
R/WC GDMA channel 2 interrupt pending register
R/WC GDMA channel 3 interrupt pending register
R/WC GDMA channel 4 interrupt pending register
R/WC GDMA channel 5 interrupt pending register
Reserved
[0] Interrupt Pending
Figure 9-7. GDMA Interrupt Pending Register
Description
GDMA CONTROLLER
Reset Value
0xXXXXXXX0
0xXXXXXXX0
0xXXXXXXX0
0xXXXXXXX0
0xXXXXXXX0
0xXXXXXXX0
1 0
I
P
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