Pci Master; Table 2-3. Pci Command Codes - Motorola MTX Series Programmer's Reference Manual

will be delayed (TRDY* will not be asserted) until the Raven has removed
some data from the FIFO. Under normal conditions, the Raven should be
able to empty the FIFO faster than the PCI bus can fill it.
PCI Configuration cycles intended for internal Raven registers will also be
delayed if Raven is busy so that control bits which may affect write posting
do not change until all write posted transactions have completed.

PCI Master

The PCI master, in conjunction with the capabilities of the PPC slave, will
attempt to move data in either single beat or burst transactions. All single
beat transactions will be subdivided into one or two 32-bit transfers,
depending on the alignment and size of the transaction. The PCI master
will attempt to transfer all burst transactions in 64-bit mode. If at any time
during the transaction the PCI target indicates it can not support 64-bit
mode, the PCI master will continue to transfer the remaining data in 32-bit
mode.
The PCI Command Codes generated by the PCI master depend on the PPC
transfer type, TBST*, and the MEM field in the MSATTx registers.
PPC Transfer Type
Write w/ Flush
Write w/ Flush
Atomic
Write w/ Kill
Graphics Write
Read
Read w/ ITM
Read w/ ITM Atomic
Graphics Read
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Table 2-3. PCI Command Codes

TBST ME
* M
x 1
x 0
0 1
1 1
x 0
Functional Description
PCI Command
0111
(Memory Write)
0011
(I/O Write)
1110
(Memory Read Line)
0110
(Memory Read)
0010
(I/O Read)
2
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