Dram Attributes Register - Motorola MTX Series Programmer's Reference Manual

DRAM Attributes Register

Address
Bit
Name
Operation
Reset
To satisfy DRAM component requirements before the memory is used at
!
start-up, software must always wait at least 500µs between the initial
setting of a bank's size bits, to a non-zero value, and the first accessing of
Warning
that bank. These settings are in the DRAM Attributes Register (offset
$FEF80010). The delay is intended to make sure that the bank has been
refreshed at least 8 times before it is used. The 500µs is sufficient as long
as the CLK Frequency Register (offset $FEF80020) is within a factor of 2
of matching the actual 60x clock frequency
ram a/b/c/d en ram a/b/c/d en enables accesses to the corresponding
block of DRAM when set, and disables them when cleared.
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$FEF80010
Programming Model
3-35
3