Sizing Dram - Motorola MTX Series Programmer's Reference Manual

DRAM control register bits. The preferred method is to be executing code
out of ROM/Flash and avoiding DRAM accesses while updating these
bits.
Since software has no way of controlling refresh accesses to DRAM, the
hardware is designed so that updating control bits coincidentally with
refreshes is not a problem. An exception to this is the ROW_ADDRESS
and COL_ADDRESS bits. It is not intended that software write to these
bits anyway.
As with DRAM, software should not change control register bits that affect
ROM/Flash while the affected Block is being accessed. This generally
means that the ROM/Flash size, base address, enable, write enable, etc. are
changed only while executing initially in the reset vector area ($FFF00000
- $FFFFFFFF).
To satisfy DRAM component requirements before the memory is used at
!
start-up, software must always wait at least 500µs between the initial
setting of a bank's size bits, to a non-zero value, and the first accessing of
Warning
that bank. These settings are in the DRAM Attributes Register (offset
$FEF80010). The delay is intended to make sure that the bank has been
refreshed at least 8 times before it is used. The 500µs is sufficient as long
as the CLK Frequency Register (offset $FEF80020) is within a factor of 2
of matching the actual 60x clock frequency.

Sizing DRAM

The following routine can be used to size DRAM for the Falcon.
Initialize the Falcon control register bits to a known state as follows:
1. Clear the isa_hole bit.
2. Make sure that ram_fref and ram_spd0,ram_spd1 are correct.
3. Set CLK_FREQUENCY to match the operating frequency.
4. Clear the refdis, rwcb bits.
5. Set the derc bit.
http://www.motorola.com/computer/literature
Software Considerations
3-59
3