Motorola MTX Series Programmer's Reference Manual page 16
Mtxa/pg4
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Also See for MTX Series:
- Service manual (66 pages) ,
- Detailed service manual (639 pages) ,
- Theory/troubleshooting manual (60 pages)
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for 180ns Devices .................................................................................................... 3-11
for 120ns Devices .................................................................................................... 3-11
for 75ns Devices ...................................................................................................... 3-12
for 45ns Devices ...................................................................................................... 3-12
Table 3-8. Error Reporting....................................................................................... 3-17
16 Bits Wide (8 Bits per Falcon) ............................................................................. 3-20
is 64 Bits Wide (32 Bits per Falcon) ....................................................................... 3-21
Table 3-11. Register Summary ................................................................................ 3-30
Table 3-12. ram spd1,ram spd0 and DRAM Type................................................... 3-34
Table 3-13. Block_A/B/C/D Configurations ........................................................... 3-36
Table 3-14. rtest encodings ...................................................................................... 3-45
Table 3-15. ROM/Flash Block A Size Encoding .................................................... 3-47
Table 3-16. rom_a_rv and rom_b_rv encoding ....................................................... 3-48
Table 3-17. Read/Write to ROM/Flash.................................................................... 3-49
Table 3-18. ROM/Flash Block B Size Encoding..................................................... 3-51
Table 3-19. Rom Speed Bit Encodings.................................................................... 3-52
Table 3-20. PowerPC 60x Address to DRAM Address Mappings.......................... 3-61
Table 3-21. Syndrome Codes Ordered by Bit in Error ............................................ 3-62
Table 3-22. Single-Bit Errors Ordered by Syndrome Code..................................... 3-63
Table 3-23. PowerPC Data to DRAM Data Mapping ............................................. 3-66
Table 4-1. IDSEL Mapping for PCI Devices ............................................................ 4-1
Table 4-2. PCI Arbitration Assignments ................................................................... 4-2
Table 4-3. Raven MPIC Interrupt Assignments ........................................................ 4-4
Table 4-4. PIB PCI/ISA Interrupt Assignments ........................................................ 4-7
Table 4-5. Reset Sources and Devices Affected........................................................ 4-9
Table 4-6. Error Notification and Handling............................................................. 4-10
Table 4-7. ROM/FLASH Bank Default.................................................................. 4-14
Table A-1. Motorola Computer Group Documents ................................................. A-1
Table A-2. Manufacturers' Documents ................................................................... A-2
Table A-3. Related Specifications ........................................................................... A-4
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