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Motorola MPC505EVB User Manual

Motorola MPC505EVB User Manual

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MPC505EVB/D
March 1997
MPC505EVB

EVALUATION BOARD

USER'S MANUAL
© MOTOROLA Inc., 1994; All Rights Reserved

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Summary of Contents for Motorola MPC505EVB

  • Page 1: Evaluation Board

    MPC505EVB/D March 1997 MPC505EVB EVALUATION BOARD USER’S MANUAL © MOTOROLA Inc., 1994; All Rights Reserved...
  • Page 2 Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.

  • Page 3: Table Of Contents

    Host Computer – EVB Interconnection ..............2-16 2.3.2 Background Mode Connector (P5)................. 2-17 2.3.3 Power Supply – EVB Interconnection..............2-18 2.3.4 RS-232C – EVB Interconnection ................2-19 2.3.5 EVB Expansion Connectors................... 2-20 2.3.6 Logic Analyzer Connectors..................2-22 2.3.7 SCSI........................2-23 MPC505EVB/D...
  • Page 4 2-1. EVB Connector, Switch, and Jumper Header Location Diagram........2-2 2-2. Power Supply Connector (P7)..................2-18 2-3. Expansion Connector P6 Pin Assignments ..............2-20 2-4. Expansion Connector P7 Pin Assignments ..............2-21 3-1. EVB Block Diagram ......................3-2 3-2. EVB Memory Map......................3-6 MPC505EVB/D...
  • Page 5 4-11. Logic Analyzer Connector POD3 Pin Assignments ............4-12 4-12. Logic Analyzer Connector POD4 Pin Assignments ............4-13 4-13. Logic Analyzer Connector POD5 Pin Assignments ............4-13 4-14. Logic Analyzer Connector POD6 Pin Assignments ............4-14 4-15. Logic Analyzer Connector POD7 Pin Assignments ............4-15 MPC505EVB/D...
  • Page 6 CONTENTS MPC505EVB/D *PRELIMINARY...

  • Page 7: Chapter 1 General Information

    CHAPTER 1 GENERAL INFORMATION 1.1 INTRODUCTION This manual provides general information, hardware preparation, installation instructions, and support information for the MPC505EVB Evaluation Board (EVB). The EVB lets you evaluate PowerPC MPC505 RISC Microcontrollers. 1.2 FEATURES EVB features include: • MPC505 MCU running at 4-33 MHz (the default is 4 MHz) •...

  • Page 8: General Description

    (as either a Motorola S-record, COFF, or ELF file) and download it to RAM. The Motorola S-record format lets you encode programs or data files in a printable format for transportation between computer systems. The transportation process can therefore be monitored and the S-records easily edited.

  • Page 9: Specifications

    GENERAL INFORMATION to 2 megabytes by replacing the devices at locations U24, U25, U27, and U28 with larger devices. The flash memory devices require +5 volts. There are a total of eight 52-pin PLCC sockets on the EVB (U19, U20, U21, U22, U29, U30, U31, and U32) for synchronous static RAM (SSRAM) devices.

  • Page 10: Equipment Required

    GENERAL INFORMATION 1.5 EQUIPMENT REQUIRED Table 1-2 lists the external equipment requirements for EVB operation. Table 1-2. External Equipment Requirements External Equipment +5 Vdc power supply SUN host computer RS-232C cable assembly MPC505EVBUM/D...

  • Page 11: Chapter 2 Hardware Preparation And Installation

    HARDWARE PREPARATION AND INSTALLATION CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION 2.1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the EVB. Chapter 6 is a description of the EVB Diagnostic Monitor (MPCdiag). 2.2 HARDWARE PREPARATION This paragraph describes the preparation of EVB components prior to use. These preparations ensure that the EVB components are properly configured.
  • Page 12 HARDWARE PREPARATION AND INSTALLATION Figure 2-1. EVB Connector, Switch, and Jumper Header Location Diagram MPC505EVBUM/D...

  • Page 13: Jumper Header Types

    HARDWARE PREPARATION AND INSTALLATION Table 2-1. Jumper Header Types Jumper Header Type Symbol Description two-pin with solder Two-pin plate through holes (without jumper header block) and strap designated as JX (X = the jumper header number). Bus wire soldered between the two pins of the plate through holes to create a short.
  • Page 14 HARDWARE PREPARATION AND INSTALLATION Table 2-2. MPFB Jumper Header Descriptions (continued) Jumper Header Type Description 3 2 1 Jumper installed on pins 1 and 2 (factory default); MCU-internal oscillator, time base, and decrementer operates as long as power is applied to the Keep alive EVB (+3.3 Vdc present on the VKAPWR2 pin of the MCU).

  • Page 15: Crystal Clock Select Header (J1)

    HARDWARE PREPARATION AND INSTALLATION 2.2.1 Crystal Clock Select Header (J1) Jumper header J1 connects the crystal clock to the MCU XTAL pin clock source. The drawing below shows the factory configuration: bus wire soldered on pins 1 and 2. This configuration selects the crystal clock source;...

  • Page 16: Clock Source Select Header (J2)

    HARDWARE PREPARATION AND INSTALLATION 2.2.2 Clock Source Select Header (J2) Use jumper header J2 to select either a crystal or clock oscillator as the MCU clock source. The drawing below shows the factory configuration: bus wire soldered on pins 2 and 3. This configuration selects the crystal clock source;...

  • Page 17: Keep Alive Power 2 Select Header (J4)

    HARDWARE PREPARATION AND INSTALLATION 2.2.4 Keep Alive Power 2 Select Header (J4) Jumper header J3 provides power to the MCU-internal oscillator, time base, and decementer modules via the MCU VKAPWR1 pin. You may use either the on-board +3.3 Vdc (jumper on J4 pins 1 and 2) or connect an external +3.3 Vdc power supply to J4 pins 2 and 3.

  • Page 18: System Clock Selection Headers (J6 And J7)

    HARDWARE PREPARATION AND INSTALLATION 2.2.6 System Clock Selection Headers (J6 and J7) Jumper headers J6 and J7 let you define the system clock source. The factory configuration (shown below) is for normal operation; a fabricated jumper on J6 and J7 pins 1 and 2. Refer to Table 2-4 for configuring the system clock source.

  • Page 19: Evb Led Descriptions

    HARDWARE PREPARATION AND INSTALLATION 2.2.7 EVB LED Descriptions There are three LEDs on the EVB. Their functions are: • LD1 – 3.3 Vdc power: ON = 3.3 Vdc power is applied to the EVB. • LD2 – Debug Mode: ON = MPC505 is in debug mode •...

  • Page 20: Evb Reset Switches

    HARDWARE PREPARATION AND INSTALLATION 2.2.9 EVB Reset Switches There are two reset switches on the EVB: • Switch SW1 lets you reset the MPC505 MCU • Switch SW2 lets you reset the EVB. 2.2.10 EVB DIP Switches There are six DIP switches on the EVB (DS1 – DS6): •...

  • Page 21: Chip Select Dip Switch (Ds1)

    HARDWARE PREPARATION AND INSTALLATION 2.2.10.1 Chip Select Dip Switch (DS1) The MPC505 MCU uses several chip selects on-board to control EVB functionality (memory and peripheral devices). You can redefine these chip selects to control external devices via the expansion connectors. To avoid conflicts between on-board and external devices, disable the appropriate chip select by setting the appropriate DS1 switch (see Table 2-6).

  • Page 22: Reset Data Dip Switches (Ds2 - Ds5)

    HARDWARE PREPARATION AND INSTALLATION 2.3.10.2 Reset Data Dip Switches (DS2 – DS5) Dip switches DS2 – DS5 are connected through 4 buffers on the MPC505 MCU data bus (D31 – D0). At RESET the MCU reads the data bus and changes its configuration according to these switches ("ON"...
  • Page 23 HARDWARE PREPARATION AND INSTALLATION Table 2-7. Data Bus Reset Configuration Word (continued) Data Configuration Effect of Effect of Function Mode Select = 1 Mode Select = 0 Default Effected During Reset During Reset Mode [9:10] IMEMBASE[0:1] IMEMBASE Block Placement Start Addr: 0x0000 0000 End Addr: 0x000F FFFF Start Addr: 0xFFF0 0000 End Addr: 0xFFFF FFFF...
  • Page 24 HARDWARE PREPARATION AND INSTALLATION Table 2-7. Data Bus Reset Configuration Word (continued) Data Configuration Effect of Effect of Function Mode Select = 1 Mode Select = 0 Default Effected During Reset During Reset Mode L-bus Memory modules L-bus Memory modules are are enabled.

  • Page 25: Dte/Dce Settings

    HARDWARE PREPARATION AND INSTALLATION 2.2.10.3 DTE/DCE Settings DS6 switch 1 lets you define which connector to use with your host computer. While DS6 switches 2 - 4 lets you define I/O connectors P2, P3, and P4 as DTE or DCE. Table 2-8 shows DS6 switch settings.

  • Page 26: Installation Instructions

    HARDWARE PREPARATION AND INSTALLATION 2.3 INSTALLATION INSTRUCTIONS The EVB is designed for table top operation. A user supplied power supply and host computer (with an RS-232C port) are required for EVB operation. 2.3.1 Host Computer – EVB Interconnection Interconnection of a host computer to the EVB is accomplished via a user supplied 25-pin flat cable assembly.

  • Page 27: Background Mode Connector (P5)

    HARDWARE PREPARATION AND INSTALLATION 2.3.2 Background Mode Connector (P5) Use connector P5 (pinouts shown below) to communicate with the EVB via the background debug mode (BDM). You may use the serial development interface (SDI) as your BDM interface. Connect one end of the SDI to your host computer and the other to connector P5. For more information about the SDI refer to the M68SDIUM Users Manual, M68SDIUM/D.

  • Page 28: Power Supply - Evb Interconnection

    HARDWARE PREPARATION AND INSTALLATION 2.3.3 Power Supply – EVB Interconnection The EVB requires +5 Vdc @ 2 amp power supply for operation. Connector P7 pin 1 is +5 Vdc; pins 2 and 3 are ground (shown in Figure 2-2). Use 16-22 AWG wire in the connector (supplied with the board).

  • Page 29: Rs-232C - Evb Interconnection

    HARDWARE PREPARATION AND INSTALLATION 2.3.4 RS-232C – EVB Interconnection Interconnection of an RS-232C compatible device to the EVB is accomplished via a user supplied 9-pin cable assembly. One end of the cable assembly is connected to either EVB port P2 or P3 (shown below).

  • Page 30: Evb Expansion Connectors

    HARDWARE PREPARATION AND INSTALLATION 2.3.5 EVB Expansion Connectors There are two expansion connectors (P6 and P8) on the EVB. The pin assignments for the expansion connectors are in Figures 2-3 and 2-4. Signal descriptions are in Appendix B. • • •...

  • Page 31: Expansion Connector P7 Pin Assignments

    HARDWARE PREPARATION AND INSTALLATION • • • +3.3 Vdc +3.3 Vdc +3.3 Vdc • • • +3.3 Vdc +3.3 Vdc +3.3 Vdc • • • BDIP~ AACK~ • • • • • • IRQ3~ VDDSYN • • • IRQ2~ IRQ6~ •...

  • Page 32: Logic Analyzer Connectors

    HARDWARE PREPARATION AND INSTALLATION 2.3.6 Logic Analyzer Connectors Use connectors POD1 through POD7 to connect a logic analyzer to the circuit being evaluated. Below are the pin assignments for the logic analyzer connectors. POD1 POD2 • • • • • •...

  • Page 33: Scsi

    HARDWARE PREPARATION AND INSTALLATION POD5 POD6 • • • • • • • • DSCK CLKOUT • • • • DSDI DSDO RESET~ SRESET~ • • • • • • • • 10 VFLS0 10 CT3 • • • • VFLS1 11 12 WP0~ CR~ 11...
  • Page 34 HARDWARE PREPARATION AND INSTALLATION 2-24 MPC505EVBUM/D...

  • Page 35: Chapter 3 Functional Description

    FUNCTIONAL DESCRIPTION CHAPTER 3 FUNCTIONAL DESCRIPTION INTRODUCTION This chapter is a functional description of the EVB and its components. EVB DESCRIPTION The EVB may be configured in either of two ways; the BCC mounted on the PFB or the BCC mounted on the target system.
  • Page 36 FUNCTIONAL DESCRIPTION Figure 3-1. EVB Block Diagram MPC505EVBUM/D...

  • Page 37: Mcu Summary

    FUNCTIONAL DESCRIPTION MCU SUMMARY The resident MC68332 Microcontroller Unit (MCU) of the BCC provides resources for designing, debugging, and evaluating MC68332 MCU based target systems and simplifies user evaluation of prototype hardware/software products. The MCU device is a 32-bit integrated microcontroller, combining high-performance data manipulation capabilities with powerful peripheral subsystems.

  • Page 38: Time Processor Unit

    FUNCTIONAL DESCRIPTION 3.3.2 Time Processor Unit The Time Processor Unit (TPU) optimizes performance of time-related activities. The TPU has a dedicated execution unit, tri-level prioritized scheduler, data storage RAM, dual time bases, and microcode ROM which drastically reduces the need for CPU intervention. The TPU controls sixteen independent, orthogonal channels;...

  • Page 39: External Bus Interface

    FUNCTIONAL DESCRIPTION 3.3.5 External Bus Interface The external bus consists of 24 address lines and a 16-bit data bus. The data bus allows dynamic sizing between 8- and 16-bit data accesses. A read-modify-write cycle (RMC) signal prevents bus cycle interruption. External bus arbitration is accomplished by a three-line handshaking interface.

  • Page 40: Evb Memory Map

    FUNCTIONAL DESCRIPTION XXX7FF (1 ) INTERNAL RAM XXX000 FFFFFF INTERNAL MODULES FFF000 OPTIONAL FPCP PFB: U5 FFE800 800000 ALTERNATE MCU INTERNAL MODULES LOCATION 7FF000 110000 /120000 OPTIONAL RAM/EPROM PFB: U2 & U4 100000 CPU32BUG EPROM BCC: U1 & U2 0E0000 CPU32BUG INTERNAL STACK 020000...

  • Page 41: I/O Connectors

    FUNCTIONAL DESCRIPTION I/O CONNECTORS There are two 64-pin expansion connectors on the BCC (P1 and P2). Through these connectors the BCC communicates with the PFB or target system. Background mode operation is available through P3 and serial communication through P4. Chapter 5 contains a description of the interface connectors pin assignments.

  • Page 42: Logic Analyzer Connectors

    FUNCTIONAL DESCRIPTION The coprocessor interface is a transparent, logical extension of the MC68332 MCU device registers and instructions. To the external environment the CPU and coprocessor execution model appear to be on the same chip. A coprocessor interface is an execution model based on sequential instruction execution by the CPU and coprocessor.

  • Page 43: Support Information

    For a complete description of the SCSI signals consult the appropriate NCR 53C90B User Manual Data Book. For a complete description of the P2,P3 signals consult the appropriate MOTOROLA M68681 User Manual Data Book. Tables 4-1 through 4-19 list pin assignments for these connectors: Table 4-1...

  • Page 44: Scsi Connector (Not Populated)

    SUPPORT INFORMATION Table 4-1. SCSI Connector (not populated) Mnemonic Signal GROUND – SDB0 SCSI DATA BUS (bit 0) Bit 0 of the SCSI bi-directional data bus lines. GROUND – SDB1 SCSI DATA BUS (bit 1) Bit 1 of the SCSI bi-directional data bus lines. GROUND –...
  • Page 45 SUPPORT INFORMATION Table 4-1. SCSI Connector (not populated) (continued) Mnemonic Signal – GROUND ATNI* ATTENTION – Active-low output signal that indicates to the target that the MPC505 has a message to send. – GROUND BUSY – Active low I/O signal that indicates the SCSI is busy. GROUND ACKNOWLEDGE –...

  • Page 46: Rs-232C I/O Connector P2 Pin Assignments

    SUPPORT INFORMATION Table 4-2. RS-232C I/O Connector P2 Pin Assignments Mnemonic Signal ADCD* DATA CARRIER DETECT – An output signal used to indicate an acceptable received line (carrier) signal has been detected. ARXD RECEIVE DATA – RS-232C serial input signal. ATXD TRANSMIT –...

  • Page 47: Rs-232C I/O Connector P3 Pin Assignments

    SUPPORT INFORMATION Table 4-3. RS-232C I/O Connector P3 Pin Assignments Mnemonic Signal BDCD* DATA CARRIER DETECT – An output signal used to indicate an acceptable received line (carrier) signal has been detected. BRXD RECEIVE DATA – RS-232C serial input signal. BTXD TRANSMIT –...

  • Page 48: Host Computer Connector P4 Pin Assignments

    SUPPORT INFORMATION Table 4-4. Host Computer Connector P4 Pin Assignments Mnemonic Signal Not Connected CTXD TRANSMIT – RS-232C serial output signal. CRXD RECEIVE DATA – RS-232C serial input signal. CRTS REQUEST TO SEND – An input signal used to request permission to transfer data.

  • Page 49: Debug Mode Connector P5 Pin Assignments

    SUPPORT INFORMATION Table 4-5. Debug Mode Connector P5 Pin Assignments Mnemonic Description VFLS0 VISIBILITY FLUSH - If VFLS0 and VFLS1 are high the MPC505 is in background debug mode. SRESET* SYSTEM RESET – Active-low, MPC505 MCU output signal that is asserted by the MCU during reset.

  • Page 50: P6 Expansion Connector Pin Assignments

    SUPPORT INFORMATION Table 4-6. P6 Expansion Connector Pin Assignments Mnemonic Signal FOE* FLASH OUTPUT ENABLE - Active low output signal that lets you read the EVB on-board flash memory. CS5* CHIP SELECT 5 Output signal that selects peripheral/memory devices at programmed addresses. A-3 A-13 A10 A20 ADDRESS BUS (bits 10 –...

  • Page 51: Input Power Connector P7 Pin Assignments

    SUPPORT INFORMATION Table 4-7. Input Power Connector P7 Pin Assignments Mnemonic Signal +5 VDC POWER – Input voltage (+5 Vdc @ 2.0 A) used by the EVB logic circuits. The "VCC" write on the board nere the coresponding pin. GROUND The "GND" write on the board nere the coresponding pin GROUND The "GND"...
  • Page 52 SUPPORT INFORMATION Table 4-8. P8 Expansion Connector Pin Assignments (continued) Mnemonic Signal A-21 Not Connected A-22 ARETRY* ADDRESS PHASE RETRY – An active-low input signal that indicates the master needs to retry its address phase. A-23 BUS GRANT – Active-low input signal that indicates that an external device has assumed control of the bus.
  • Page 53 SUPPORT INFORMATION Table 4-8. P8 Expansion Connector Pin Assignments (continued) Mnemonic Signal BURST INHIBIT – Active-low input signal that indicates the slave does not support burst mode. C-5, C-6 IRQ3* IRQ2* INTERRUPT REQUEST (3, 2) – Prioritized active low input lines that requests MCU synchronous interrupts.

  • Page 54: Logic Analyzer Connector Pod1 Pin Assignments

    SUPPORT INFORMATION Table 4-9. Logic Analyzer Connector POD1 Pin Assignments Mnemonic Signal 1, 2 Not Connected TRANSFER START – An active-low output signal that indicates the start of a bus cycle. FOE* FLASH OUTPUT ENABLE - Active low output signal that lets you read the EVB on-board flash memory.

  • Page 55: Logic Analyzer Connector Pod4 Pin Assignments

    SUPPORT INFORMATION Table 4-12. Logic Analyzer Connector POD4 Pin Assignments Mnemonic Signal 1 – 3 Not Connected 4 – 19 D0 – D15 DATA BUS (bits 0 15) – Bi-directional data pins. GROUND Table 4-13. Logic Analyzer Connector POD5 Pin Assignments Mnemonic Signal 1 –...

  • Page 56: Logic Analyzer Connector Pod6 Pin Assignments

    SUPPORT INFORMATION Table 4-14. Logic Analyzer Connector POD6 Pin Assignments Mnemonic Signal 1 – 3 Not Connected CLKOUT SYSTEM CLOCK OUT – Output signal that is the MPC505 MCU internal system clock. RESET* RESET – Active-low, input signal that resets the MPC505 MCU. SRESET* SYSTEM RESET –...

  • Page 57: Logic Analyzer Connector Pod7 Pin Assignments

    SUPPORT INFORMATION Table 4-15. Logic Analyzer Connector POD7 Pin Assignments Mnemonic Signal 1, 2 Not Connected CLKOUT SYSTEM CLOCK OUT – Output signal that is the MPC505 MCU internal system clock. BURST BURST – Active low indicates a burst cycle. TEA* TRANSFER ERROR ACKNOWLEDGE –...
  • Page 58 SUPPORT INFORMATION 4-16 MPC505EVBUM/D...

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