Motorola MTX Series Programmer's Reference Manual page 99

Raven PCI Host Bridge & Multi-Processor Interrupt Controller
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REG Register Number. For PCI Configuration cycles, bits 7 through 2
identify the target double word within the target function's configuration
space. Bits 1 and 0 must always be zero for a type 0 configuration cycle.
These bits are copied to the PCI AD bus during the address phase on a
Configuration cycle.This field must be all zeros for Special cycles.
FUN Function Number. For PCI Configuration cycles, bits 10 through 8
identify the function number within the target physical PCI device. These
bits are copied to the PCI AD bus during the address phase on a
Configuration cycle. This field must be all ones for Special cycles.
DEV Device Number. For PCI Configuration cycles, bits 15 through 11
identify the target physical PCI device number. Raven does a decode of the
Device Number field to assert the appropriate IDSEL line. Values of $01
through $0a and $1f are illegal entries for the device number. The Raven
will drive all 0's in bit position AD11 through AD31 if a illegal device id
is initialized into the configuration address register. A value of $0B sets
PCI AD bit 11 (IDSEL 11) during the address phase of a Configuration
cycle. A value of $0C sets AD bit 12. As the device number increments the
AD bit increments until a the value of $1E sets AD bit 30. A value of $00
in device number field will select AD bit 31. The device number field must
be all ones for Special cycles.
BUS Bus Number. For PCI Configuration cycles or Special cycles, bits
23 through 16 identify the bus number. Raven is always connected to PCI
bus number zero. Bits 23 through 16 must be zero for a Configuration
cycle or Special cycle. Raven will execute a type 1 translation cycle if the
bus number is set to a value not equal to zero.
EN Enable. Bit 31 must be set to a one, enabling the translation of a
subsequent host bus I/O access to the CONFIG_DATA register into a
configuration access on the PCI bus. If bit 31 is zero and the processor
initiates an I/O read from or write to the CONFIG_DATA register, the
transaction is passed through to the PCI bus as a PCI I/O transaction.
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