Current Task Priority Level - Motorola MTX Series Programmer's Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2

Current Task Priority Level

Architectural Notes
2-78
external interrupt source 0 directly through to processor zero. During
interrupt controller initialization this channel should be programmed for
mixed mode in order to take advantage of the interrupt delivery modes.
Each processor has a separate Current Task Priority Level register. The
system software uses this register to indicate the relative priority of the task
running on the corresponding processor. The interrupt controller will not
deliver an interrupt to a processor unless it has a priority level which is
greater than the current task priority level of that processor. This value is
also used in determining the destination for interrupts which are delivered
using the distributed deliver mode.
The hardware and software overhead required to update the task priority
register synchronously with instruction execution may far outweigh the
anticipated benefits of the task priority register. To minimize this
overhead, the interrupt controller architecture should allow the task
priority register to be updated asynchronously with respect to instruction
execution. Lower priority interrupts may continue to occur for an
indeterminate number of cycles after the processor has updated the task
priority register. If this is not acceptable, the interrupt controller
architecture should recommend that, if the task priority register is not
implemented with the processor, the task priority register should be
updated only when the processor enter or exits an idle state.
Only when the task priority register is integrated within the processor,
(such that it can be accessed as quickly as the MSRee bit, for example),
should the architecture require the task priority register to be updated
synchronously with instruction execution.
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