Processor 0 External Cache Control Register (P0Xccr) - Motorola MTX Series Programmer's Reference Manual

Note
SXC_RST_ System External Cache Reset. When this bit is cleared, it
invalidates all tags and holds the cache in a reset condition.
Note
SXC_MI_ System External Cache Miss Inhibit. When this bit is cleared,
it prevents line fills on cache misses.
Software should never clear more than one of these bits at the same time.
!
If more than one is cleared at the same time, the Glance pair behaves
indeterminately.
Warning

Processor 0 External Cache Control Register (P0XCCR)

The Processor 0 External Cache Control Register is accessed via the
RD[32:39] data lines of the upper Falcon device. This register is not
implemented for systems without In-line Cache. This 8-bit register is
defined as follows:
Register
Bit 0
Field
Operation R/W
Reset 0
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This operation causes the Glance pair to request and hold the
MPC bus until it has completed the flush operation
(approximately 4100 clock cycles). This may be an issue if other
devices cannot wait that long to acquire MPC bus mastership.
Current Glance devices do not hold the cache in a reset condition;
however, the tag invalidate function still operates.
Processor 0 External Cache Control Register - FEF88100h
1 2
R/W R/W R/W
0 0
3 4 5
R/W R/W
0 X X
Programming Model
6 7
R/W R/W
X X
1-21
1