Motorola MTX Series Programmer's Reference Manual page 28

Table 1-3. CHRP Memory Map Example (Continued)
Processor Address
Start End
FE80 0000 FEF7 FFFF
FEF8 0000 FEF8 FFFF
FEF9 0000 FEFE FFFF
FEFF 0000 FEFF FFFF
FF00 0000 FF7F FFFF
FF80 0000 FF8F FFFF
FF50 0000 FFEF FFFF
FFF0 0000 FFFF FFFF
Notes
1. Programmable via Falcon chipset.
2. To enable the Processor-hole area, program the Falcon chipset to
3. Programmable via Raven ASIC.
4. CHRP requires the starting address for the PCI memory space to be
5. Programmable via Raven ASIC for either contiguous or spread-I/O
6. The first 1MB of ROM/FLASH Bank A appears at this range after
7. The only method to generate a PCI Interrupt Acknowledge cycle
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Size
7.5M Reserved
64K Falcon Registers
384K Reserved
64K Raven Registers
4M ROM/FLASH Bank A
1M ROM/FLASH Bank B
6M Reserved
1M ROM/FLASH Bank A or Bank B
ignore 0x000A0000 - 0x000BFFFF address range and program the
Raven to map this address range to PCI memory space.
256MB-aligned.
mode.
a reset if the rom_b_rv control bit is cleared. If the rom_b_rv
control bit is set then this address range maps to ROM/FLASH Bank
B.
(8259 IACK) is to perform a read access to the Raven's PIACK
register at 0xFEFF0030.
Programming Model
Definition
1
7
1,6
1,6
6
1-7