Processor 1 External Cache Control Register (P1Ccr) - Motorola MTX Series Programmer's Reference Manual

Board Description and Memory Maps
1

Processor 1 External Cache Control Register (P1CCR)

Register
Bit 0
Field
Operation R/W
Reset 0
1-22
P0XC_CFG Processor 0 External Cache Configuration Access Mode.
When this bit is set, it maps the Processor 0's external cache in
Configuration Access Mode. Refer to the IBM15-C700A SLC User's
Manual for details.
P0XC_DIS_ Processor 0 External Cache Disable. When this bit is
cleared, it disables this cache from responding to any bus cycles.
The Processor 1 External Cache Control Register is accessed via the
RD[32:39] data lines of the upper Falcon device. This register is not
implemented for systems without In-line Cache. This 8-bit register is
defined as follows:
Processor 1External Cache Control Register - FEF88200h
1 2
R/W R/W
0 0
P1XC_CFG Processor 1External Cache Configuration Access Mode.
When this bit is set, it maps the Processor 1's external cache in
Configuration Access Mode. Refer to the IBM15-C700A SLC User's
Manual for details.
P1XC_DIS_ Processor 1External Cache Disable. When this bit is cleared,
it disables this cache from responding to any bus cycles.
3 4
R/W R/W R/W
0 X
Computer Group Literature Center Web Site
5 6
R/W R/W
X X X
7