Table 4-6. Error Notification And Handling - Motorola MTX Series Programmer's Reference Manual

Programming Details
4
Cause
Single-bit ECC
Double-bit ECC
MPC Bus Time Out
PCI Target Abort
PCI Master Abort
PERR# Detected
SERR# Detected
4-10
Note
The TEA* signal is not used at all by the MTX series. The
following table summarizes how the hardware errors are handled
by the MTX series:

Table 4-6. Error Notification and Handling

Action
Store: Write corrected data to memory
Load: Present corrected data to the MPC master
Generate interrupt via Raven MPIC if so enabled
Store: Terminate the bus cycle normally without writing to DRAM
Load: Present un-corrected data to the MPC master
Generate interrupt via Raven MPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Store: Discard write data and terminate bus cycle normally
Load: Present undefined data to the MPC master
Generate interrupt via Raven MPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Store: Discard write data and terminate bus cycle normally
Load: Return all 1's and terminate bus cycle normally
Generate interrupt via Raven MPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Store: Discard write data and terminate bus cycle normally
Load: Return all 1's and terminate bus cycle normally
Generate interrupt via Raven MPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Generate interrupt via Raven MPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Generate interrupt via Raven MPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
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