End-Of-Interrupt Registers - Motorola MTX Series Programmer's Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2

End-of-Interrupt Registers

Offset
Bit
Name
Operation
Reset
Programming Notes
External Interrupt Service
2-74
On PowerPC-based systems, Interrupt Acknowledge is implemented as a
read request to a memory-mapped Interrupt Acknowledge register.
Reading the Interrupt Acknowledge register returns the interrupt vector
corresponding to the highest priority pending interrupt. Reading this
register also has the following side effects.
The associated bit in the Interrupt Pending Register is cleared.
Reading this register will update the In-Service register.
Reading this register without a pending interrupt will return a value of $FF
hex.
3 3 2 2 2 2 2 2 2
1 0 9 8 7 6 5 4 3
R
$00
EOI END OF INTERRUPT. There is one EOI register per processor.
EOI Code values other than 0 are currently undefined. Data values written
to this register are ignored; zero is assumed. Writing to this register signals
the end of processing for the highest priority interrupt currently in service
by the associated processor. The write operation will update the In-Service
register by retiring the highest priority interrupt. Reading this register
returns zeros.
The following summarizes how an external interrupt is serviced:
1. An external interrupt occurs.
Processor 0 $200B0
Processor 1 $210B0
2 2 2 1 1 1 1 1 1
2 1 0 9 8 7 6 5 4
R
$00
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1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2 1 0
R R
$00 $0
EOI
W
$0