Ecc Control Register - Motorola MTX Series Programmer's Reference Manual

Falcon ECC Memory Controller Chip Set
3

ECC Control Register

Address
Bit
Name
Operation
Reset
3-38
prescale counter produces a 1 MHz output. The output of the chip prescale
counter is used by the refresher/scrubber and the 32-bit counter. After
power-up, this register is initialized to $42 (for 66MHz).
por por is set by the occurrence of power up reset. It is cleared by writing
a one to it. Writing a 0 to it has no effect.
refdis When set, refdis causes the refresher and all of its associated
counters and state machines to be cleared and maintained that way until
refdis is removed (cleared). If a refresh cycle is in process when refdis is
updated by a write to this register, the update does not take effect until the
refresh cycle has completed. This prevents the generation of illegal cycles
to the DRAM when refdis is updated.
rwcb, When set, causes reads and writes to DRAM from the PowerPC 60x
bus to access check-bit data rather than normal data. The data path used for
this mode is DH24-31 for check-bit data controlled by the upper Falcon,
and DL24-31 for check-bit data controlled by the lower Falcon. Each 8-bit
check-bit location services 64 bits of normal data. The 64 bits of data are
all within the same Falcon. Each Falcon provides every other 32 bits of
data in the normal mode. The figure below shows the relationship between
normal data and check-bit data.
$FEF80028
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