Isa Dma Channels - Motorola MTX Series Programmer's Reference Manual

Programming Details
4

ISA DMA Channels

Exceptions
Sources of Reset
4-8
3. After a reset, all ISA IRQ interrupt lines default to edge-sensitive
mode.
4. Interrupts from Z8536 and Z85230 devices are externally wire-
ORed. External logic will determine which device to acknowledge
during a pseudo IACK cycle. The Z8536 CIO has higher priority
than the Z85230 ESCC. This IRQ MUST be programmed for level-
sensitive mode.
5. These PCI interrupts are routed to the ISA interrupts by
programming the PRIQ Route Control Registers in the PIB. The
PCI to ISA interrupt assignments in this table are suggested. Each
ISA IRQ to which a PCI interrupt is routed to MUST be
programmed for level-sensitive mode. Use this routing for PCI
interrupts only when the Raven MPIC is either not present or not
used.
6. The Raven MPIC, when present, should be used for these interrupts.
Refer to Chapter 1, Board Description and Memory
on the ISA DMA channels.
There are five potential sources of reset on the MTX series. They are:
1. Power-On Reset
2. RESET Switch
3. Watchdog Timer Reset via the MK48T59 Timekeeper device
4. Port 92 Register via the PIB
Maps, for information
Computer Group Literature Center Web Site